scholarly journals Semiconductor Integrated Circuit Technology and Micromachining

Sensors ◽  
2008 ◽  
pp. 107-168 ◽  
Author(s):  
Wen H. Ko ◽  
James T. Suminto
Keyword(s):  
Integrated Circuit ◽  
Circuit Technology

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

PERFORMANCE AT THE EDGE: GALLIUM ARSENIDE AND SILICON ICs FOR OPTICAL ELECTRONICS

1991 ◽  
Vol 02 (03) ◽  
pp. 147-162 ◽  
Author(s):  
ROBERT G. SWARTZ
Keyword(s):  
Gallium Arsenide ◽  
Optical Communication ◽  
Optical Communications ◽  
Integrated Circuit ◽  
High Performance ◽  
Compound Semiconductor ◽  
Performance Curve ◽  
Semiconductor Technology ◽  
Market Trends ◽  
Circuit Technology

Compound semiconductor technology is rapidly entering the mainstream, and is quickly finding its way into consumer applications where high performance is paramount. But silicon integrated circuit technology is evolving up the performance curve, and CMOS in particular is consuming ever more market share. Nowhere is this contest more clearly evident than in optical communications. Here applications demand performance ranging from a few hundreds of megahertz to multi-gigahertz, from circuits containing anywhere from tens to tens of thousands of devices. This paper reviews the high performance electronics found in optical communication applications from a technology standpoint, illustrating merits and market trends for these competing, yet often complementary IC technologies.

scholarly journals Design and Development of a 3dB Quadrature Patch Hybrid Coupler

2018 ◽  
Vol 7 (2.6) ◽  
pp. 217
Author(s):  
B Sekharbabu ◽  
K Narsimha Reddy ◽  
S Sreenu
Keyword(s):  
Integrated Circuit ◽  
High Frequency ◽  
Return Loss ◽  
Coupling Factor ◽  
Power Combiners ◽  
Measurement Results ◽  
Structure Simulation ◽  
Hybrid Coupler ◽  
Port Device ◽  
Circuit Technology

In this paper a -3 dB, 90-degreephase shift RF quadrature patch hybrid coupler is designed to operate at 2.4GHz. Hybrid coupler is a four-port device, that’s accustomed split a signaling with a resultant 90degrees’ section shift between output signals whereas maintaining high isolation between the output ports. The RF quadrature patch hybrid coupler is used in various radio frequency applications including mixers, power combiners, dividers, modulators and amplifiers. The desired hybrid coupler is designed using FR-4 substrate with 1.6mm height in High Frequency Structure Simulation (HFSS) and the same is fabricated and tested. The designed Hybrid coupler is examined in terms of parameters like insertion Loss, coupling factor and return Loss. The simulation and measurement results are compared. Major advantages of the RF quadrature patch hybrid couplers are that they are compatible with integrated circuit technology.

Conversion Method of Description Files in Structural Testing of Digital Circuit

2013 ◽  
Vol 427-429 ◽  
pp. 1285-1288
Author(s):  
Kang Yi Wang
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Structural Testing ◽  
Digital Logic ◽  
Continuous Development ◽  
Program Correctness ◽  
Testing Program ◽  
Circuit Technology

With the continuous development of large-scale integrated circuit technology, the importance of structural testing and testability design for digital logic circuit has become increasingly evident. In the testing domain, Bench is the most commonly used formats to describe a measured circuit. In order to test the measured circuit using computer, files with various formats must be converted to a netlist file which can be identified by computer. Lev format is a common netlist file. This paper mainly discusses how to convert the Bench file into Lev file, and it is proved by testing program correctness and robustness.

An n-channel Si-gate integrated circuit technology

1975 ◽  
Author(s):  
J.T. Clemens ◽  
R.H. Doklan ◽  
J.J. Nolen
Keyword(s):  
Integrated Circuit ◽  
Circuit Technology

THE DEPOSITION AND CONTROL OF SELF ASSEMBLED SILICON NANO ISLANDS ON CRYSTALLINE SILICON

2008 ◽  
Vol 18 (04) ◽  
pp. 901-910
Author(s):  
RAGNAR KIEBACH ◽  
ZHENRUI YU ◽  
MARIANO ACEVES-MIJARES ◽  
DONGCAI BIAN ◽  
JINHUI DU
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuit ◽  
Crystalline Silicon ◽  
Substrate Surface ◽  
Chemical Vapor ◽  
High Density ◽  
Transmission Electron ◽  
Pressure Chemical ◽  
And Control ◽  
Circuit Technology

The formation of nano sized Si structures during the annealing of silicon rich oxide (SRO) films was investigated. These films were synthesized by low pressure chemical vapor deposition (LPCVD) and used as precursors, a post-deposition thermal annealing leads to the formation of Si nano crystals in the SiO 2 matrix and Si nano islands ( Si nI ) at c-Si /SRO interface. The influences of the excess Si concentration, the incorporation of N in the SRO precursors, and the presence of a Si concentration gradient on the Si nI formation were studied. Additionally the influence of pre-deposition substrate surface treatments on the island formation was investigated. Therefore, the substrate surface was mechanical scratched, producing high density of net-like scratches on the surface. Scanning electron microscopy (SEM) and high resolution transmission electron microscopy (HRTEM) were used to characterize the synthesized nano islands. Results show that above mentioned parameters have significant influences on the Si nIs . High density nanosized Si islands can epitaxially grow from the c-Si substrate. The reported method is very simple and completely compatible with Si integrated circuit technology.

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