Hardware implementations of artificial neural networks

Author(s):  
D. Corso
VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-25 ◽  
Author(s):  
Saumil G. Merchant ◽  
Gregory D. Peterson

Dedicated hardware implementations of artificial neural networks promise to provide faster, lower-power operation when compared to software implementations executing on microprocessors, but rarely do these implementations have the flexibility to adapt and train online under dynamic conditions. A typical design process for artificial neural networks involves offline training using software simulations and synthesis and hardware implementation of the obtained network offline. This paper presents a design of block-based neural networks (BbNNs) on FPGAs capable of dynamic adaptation and online training. Specifically the network structure and the internal parameters, the two pieces of the multiparametric evolution of the BbNNs, can be adapted intrinsically, in-field under the control of the training algorithm. This ability enables deployment of the platform in dynamic environments, thereby significantly expanding the range of target applications, deployment lifetimes, and system reliability. The potential and functionality of the platform are demonstrated using several case studies.


Author(s):  
Kobiljon Kh. Zoidov ◽  
◽  
Svetlana V. Ponomareva ◽  
Daniel I. Serebryansky ◽  
◽  
...  

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