Multiprocessor Systems Design: Reliability Analysis of Multistage Interconnection Network

2019 ◽  
pp. 858-864
Author(s):  
Amit Prakash ◽  
Dilip Kumar Yadav
Keyword(s):  
Reliability Analysis ◽  
Interconnection Network ◽  
Systems Design ◽  
Multiprocessor Systems ◽  
Multistage Interconnection Network ◽  
Design Reliability

Reliability Analysis of the Generalized Exchanged Hypercube

2020 ◽  
Vol 30 (02) ◽  
pp. 2050009
Author(s):  
Qifan Zhang ◽  
Liqiong Xu ◽  
Weihua Yang ◽  
Shanshan Yin
Keyword(s):  
Fault Tolerance ◽  
Reliability Analysis ◽  
Network Structure ◽  
Complete Graph ◽  
Interconnection Network ◽  
Natural Extension ◽  
Graph Model ◽  
Text Component ◽  
Optimal Formula

Let [Formula: see text] be a non-complete graph, a subset [Formula: see text] is called a [Formula: see text]-component cut of [Formula: see text], if [Formula: see text] is disconnected and has at least [Formula: see text] components. The cardinality of the minimum [Formula: see text]-component cut is the [Formula: see text]-component connectivity of [Formula: see text] and is denoted by [Formula: see text]. The [Formula: see text]-component connectivity is a natural extension of the classical connectivity. As an application, the [Formula: see text]-component connectivity can be used to evaluate the reliability and fault tolerance of an interconnection network structure based on a graph model. In a previous work, E. Cheng et al. obtained the [Formula: see text]-component connectivity of the generalized exchanged hypercube [Formula: see text] for [Formula: see text] and [Formula: see text]. In this paper, we continue the work and determine that [Formula: see text] for [Formula: see text]. Moreover, we show that every optimal [Formula: see text]-component cut of [Formula: see text] is trivial for [Formula: see text] and [Formula: see text].

scholarly journals Design and Implementation of Rearrangable Non-Blocking Switching Network in VLSI

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2858-2863
Keyword(s):  
Interconnection Network ◽  
The Other ◽  
Switching Network ◽  
Low Latency ◽  
Multistage Interconnection Network ◽  
Design And Implementation ◽  
Benes Network ◽  
Benes Networks

The main goal of this article is to implement an effective Non-Blocking Benes switching Network. Benes Switching Network is designed with the uncomplicated switch modules & it’s have so many advantages, small latency, less traffic and it’s required number of switch modules. Clos and Benes networks are play a key role in the class of multistage interconnection network because of their extensibility and mortality. Benes network provides a low latency when compare with the other networks. 8x8 Benes non blocking switching network is designed and synthesized with the using of Xilinx tool 12.1.

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