An Efficient Design of a Reversible Fault Tolerant $$n$$ -to-2 $$^n$$ Sequence Counter Using Nano Meter MOS Transistors

2015 ◽  
pp. 455-462
Author(s):  
Md. Shamsujjoha ◽  
Sirin Nahar Sathi ◽  
Golam Sorwar ◽  
Fahmida Hossain ◽  
Md. Nawab Yousuf Ali ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Efficient Design ◽  
Mos Transistors ◽  
Sequence Counter

Cost Efficient Design of Fault Tolerant Geo-Distributed Data Centers

2017 ◽  
Vol 14 (2) ◽  
pp. 289-301 ◽  
Author(s):  
Rakesh Tripathi ◽  
S. Vignesh ◽  
Venkatesh Tamarapalli ◽  
Deep Medhi
Keyword(s):  
Data Centers ◽  
Fault Tolerant ◽  
Distributed Data ◽  
Efficient Design ◽  
Cost Efficient

Design of Optimal CMOS Analog Amplifier Circuits Using a Hybrid Evolutionary Optimization Technique

2017 ◽  
Vol 27 (02) ◽  
pp. 1850029 ◽  
Author(s):  
Bishnu Prasad De ◽  
Kanchan Baran Maji ◽  
Rajib Kar ◽  
Durbadal Mandal ◽  
Sakti Prasad Ghoshal
Keyword(s):  
Power Dissipation ◽  
Optimization Problems ◽  
Optimization Technique ◽  
Optimization Method ◽  
Vlsi Circuits ◽  
Optimal Designs ◽  
Efficient Design ◽  
Mos Transistors ◽  
Evolutionary Technique ◽  
Random Particle

This paper proposes an efficient design technique for two commonly used VLSI circuits, namely, CMOS current mirror load-based differential amplifier circuit and CMOS two-stage operational amplifier. The hybrid evolutionary method utilized for these optimal designs is random particle swarm optimization with differential evolution (RPSODE). Random PSO utilizes the weighted particles for monitoring the search directions. DE is a robust evolutionary technique. It has demonstrated an exclusive performance for the optimization problems which are continuous and global but suffers from the uncertainty issues. PSO is a robust optimization method but suffers from sub-optimality problem. This paper effectively hybridizes the random PSO and DE to remove the limitations related to both the techniques individually. In this paper, RPSODE is employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained from RPSODE technique are validated in SPICE environment. SPICE-based simulation results justify that RPSODE is a much better technique than other formerly reported methods for the designs of the above mentioned circuits in terms of MOS area, gain, power dissipation, etc.

Efficient design of fault tolerant tiles in QCA

2014 ◽  
Author(s):  
Bibhash Sen ◽  
Aman Agarwal ◽  
Rajdeep Kumar Nath ◽  
Rijoy Mukherjee ◽  
Biplab K Sikdar
Keyword(s):  
Fault Tolerant ◽  
Efficient Design

Optimized fault tolerant designs of the reversible barrel shifters using low power MOS transistors

2015 ◽  
Vol 14 (3) ◽  
pp. 726-746 ◽  
Author(s):  
Md. Shamsujjoha ◽  
Fahmida Hossain ◽  
Md. Nawab Yousuf Ali ◽  
Hafiz Md. Hasan Babu
Keyword(s):  
Low Power ◽  
Fault Tolerant ◽  
Mos Transistors

Performance Comparison of Survival Routing Mechanisms in Wireless Mesh Networks

2013 ◽  
Vol 760-762 ◽  
pp. 623-627
Author(s):  
Yu Huai Peng ◽  
Yin Peng Yu ◽  
Cun Qian Yu ◽  
Qing Yang Song ◽  
Fei Wang
Keyword(s):  
Wireless Mesh Networks ◽  
Performance Metrics ◽  
Mesh Networks ◽  
Fault Tolerant ◽  
Performance Comparison ◽  
Wireless Channel ◽  
Delivery Ratio ◽  
Efficient Design ◽  
Traffic Pattern ◽  
Wireless Mesh

This paper addresses the fault-tolerant mechanisms in Wireless mesh networks (WMNs), and designs a C++ based simulation platform to measure the performance of different fault-tolerant mechanisms. A comprehensive performance evaluation of network coding tree algorithm (NCT), 1+1 scheme and 1: N scheme in WMNs is conducted. Performance metrics, such as packet delivery ratio, resource redundancy degree, end-to-end delay, and useful throughput ratio, are investigated. The simulation results and performance analysis reveal that how wireless channel quality can influence the performance of WMNs and how different fault-tolerant mechanisms can be efficient and effective for latency-sensitive applications in WMNs. The results can also provide the enlightening insights for efficient design of fault-tolerant routing protocols for many-to-one traffic pattern in WMNs.

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