Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge

2019 ◽  
Vol 94 (6) ◽  
pp. 841-849 ◽  
Author(s):  
P K Singh ◽  
K Baral ◽  
S Kumar ◽  
S Chander ◽  
S Jit
2001 ◽  
Vol 24 (3) ◽  
pp. 187-199 ◽  
Author(s):  
R. Marrakh ◽  
A. Bouhdada

In this paper, we present a drain current model for stressed short-channel MOSFET's. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time.


2017 ◽  
Vol 64 (8) ◽  
pp. 3502-3507 ◽  
Author(s):  
In Huh ◽  
Sangchun Park ◽  
Mincheol Shin ◽  
Woo Young Choi

2019 ◽  
Vol 9 (2) ◽  
pp. 291-297
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Ahmed Bouziane ◽  
Benjamin Iñiguez

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.


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