1μA IQ synchronous boost converter extends battery life in portable devices

2015 ◽  
pp. 239-240
Author(s):  
Goran Perica
Keyword(s):  
Boost Converter ◽  
Battery Life ◽  
Portable Devices

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

scholarly journals LTTng CLUST: A System-Wide Unified CPU and GPU Tracing Tool for OpenCL Applications

2015 ◽  
Vol 2015 ◽  
pp. 1-14 ◽  
Author(s):  
David Couturier ◽  
Michel R. Dagenais
Keyword(s):  
Application Programming Interface ◽  
Third Party ◽  
Battery Life ◽  
Portable Devices ◽  
Processing Unit ◽  
Central Processing ◽  
Application Programming ◽  
Graphical Processing ◽  
Performance Analysis Tools ◽  
Programming Interface

As computation schemes evolve and many new tools become available to programmers to enhance the performance of their applications, many programmers started to look towards highly parallel platforms such as Graphical Processing Unit (GPU). Offloading computations that can take advantage of the architecture of the GPU is a technique that has proven fruitful in recent years. This technology enhances the speed and responsiveness of applications. Also, as a side effect, it reduces the power requirements for those applications and therefore extends portable devices battery life and helps computing clusters to run more power efficiently. Many performance analysis tools such as LTTng, strace and SystemTap already allow Central Processing Unit (CPU) tracing and help programmers to use CPU resources more efficiently. On the GPU side, different tools such as Nvidia’s Nsight, AMD’s CodeXL, and third party TAU and VampirTrace allow tracing Application Programming Interface (API) calls and OpenCL kernel execution. These tools are useful but are completely separate, and none of them allow a unified CPU-GPU tracing experience. We propose an extension to the existing scalable and highly efficient LTTng tracing platform to allow unified tracing of GPU along with CPU’s full tracing capabilities.

scholarly journals Design & Implementation of Power Bank using Supercapacitor

2019 ◽  
Vol 9 (1) ◽  
pp. 1124-1228
Keyword(s):  
Power Flow ◽  
Storage Device ◽  
Battery Life ◽  
Portable Devices ◽  
Portable Power ◽  
Control Power ◽  
Design And Implementation ◽  
Long Time ◽  
A Charge ◽  
Flow Power

Portable power banks are comprised of battery in a case with a circuit to control power flow. Power banks are becoming increasingly popular because the battery life of phones, tablets and portable media players is ex ceeded by the number of time gadgets used in aday. In this paper, the design and implementation of power bank using supercapacitors as a charge storage device is presented. Existing power banks use batteries to store charges and it takes a long time to charge completely. In this work, batteries are replaced with supercapacitors to take advantage of its quick charging and slow discharging feature. Supercapacitors are charged using charging and regulation circuit. An output regulator circuit delivers the necessary power for charging portable devices. A display is also implemented using a PIC microcontroller for monitoring.

scholarly journals Crystal Orientation Mapping of Copper Interconnects using EBSD

2000 ◽  
Vol 8 (6) ◽  
pp. 36-38
Author(s):  
Keith Dicks
Keyword(s):  
Electron Backscatter Diffraction ◽  
Semiconductor Industry ◽  
Copper Interconnects ◽  
Battery Life ◽  
Portable Devices ◽  
Resolution Electron ◽  
Grain Orientations ◽  
Electron Microscopes ◽  
Scanning Electron Microscopes ◽  
Backscatter Diffraction

The semiconductor industry is committed to introducing copper interconnects in place of aluminum for the latest generation of semiconductor devices. With its greater current carrying capacity, the use of copper should enable further reductions in device geometry, power consumption and heat generation, and lead to higher performance and longer battery life in portable devices.Grain orientations, crystal log raphic ‘texture’ trends and boundary types are crucial in determining properties such as electrical resistively, strength and corrosion resistance. These parameters may be implicated both in the performance of the device and in failure mechanisms, which are of great importance in determining reliability.Our work demonstrates that high-resolution electron backscatter diffraction (EBSD) is now both possible and routinely achievable using both hot and cold field emission gun scanning electron microscopes (FEGSEMs). Our results demonstrate that EBSD can be successfully used to map grain orientation and to reveal and classify grain boundaries for this application.

scholarly journals A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-7
Author(s):  
Hou-Ming Chen ◽  
Robert C. Chang ◽  
Kuang-Hao Lin
Keyword(s):  
High Efficiency ◽  
Power Conversion ◽  
Cmos Technology ◽  
Pulse Frequency ◽  
Boost Converter ◽  
Battery Life ◽  
Pulse Frequency Modulation ◽  
Load Range ◽  
Load Current ◽  
The Cost

This paper presents a high-efficiency monolithic dc-dc PFM boost converter designed with a standard TSMC 3.3/5V 0.35 μm CMOS technology. The proposed boost converter combines the parallel power MOS technique with pulse-frequency modulation (PFM) technique to achieve high efficiency over a wide load current range, extending battery life and reducing the cost for the portable systems. The proposed parallel power MOS controller and load current detector exactly determine the size of power MOS to increase power conversion efficiency in different loads. Postlayout simulation results of the designed circuit show that the power conversion is 74.9–90.7% efficiency over a load range from 1 mA to 420 mA with 1.5 V supply. Moreover, the proposed boost converter has a smaller area and lower cost than those of the existing boost converter circuits.

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