A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs
2004 ◽
Vol 28
(5-6)
◽
pp. 291-301
◽
1995 ◽
Vol 21
(11)
◽
pp. 865-880
◽
2015 ◽
Vol 10
(7)
◽
pp. 790-813
◽
Keyword(s):
2011 ◽
Vol 3
◽
pp. 1120-1125
◽
Keyword(s):
2011 ◽
Vol 5
(2)
◽
pp. 123
◽