A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver

Integration ◽

10.1016/j.vlsi.2007.04.001 ◽

2008 ◽

Vol 41 (2) ◽

pp. 161-170 ◽

Author(s):

L. Bissi ◽

P. Placidi ◽

G. Baruffa ◽

A. Scorzoni

Keyword(s):

Viterbi Decoder ◽

Decoder Architecture

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Power-Efficient Viterbi Decoder Architecture and Field Programmeble Gate Arrays Fpga Implementation

Istanbul University - Journal of Electrical & Electronics Engineering ◽

10.5152/iujeee.2018.1809 ◽

2018 ◽

Vol 18 (1) ◽

pp. 52-59

Author(s):

Burcu Ozbay ◽

◽

Serap Cekli ◽

Keyword(s):

Fpga Implementation ◽

Viterbi Decoder ◽

Power Efficient ◽

Gate Arrays ◽

Decoder Architecture

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A New Low-Power and High Speed Viterbi Decoder Architecture

Ubiquitous Convergence Technology - Lecture Notes in Computer Science ◽

10.1007/978-3-540-71789-8_29 ◽

2007 ◽

pp. 283-291

Author(s):

Chang-Jin Choi ◽

Sang-Hun Yoon ◽

Jong-Wha Chong ◽

Shouyin Lin

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Decoder Architecture

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Viterbi decoder architecture for interleaved convolutional code

Conference Record of the Thirty-Sixth Asilomar Conference on Signals Systems and Computers 2002 ACSSC-02 ◽

10.1109/acssc.2002.1197117 ◽

2003 ◽

Author(s):

Jun Jin Kong ◽

K.K. Parhi

Keyword(s):

Convolutional Code ◽

Viterbi Decoder ◽

Decoder Architecture

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A Viterbi decoder architecture based on parallel processing elements

[Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition ◽

10.1109/glocom.1990.116709 ◽

2002 ◽

Author(s):

S.R. Meier

Keyword(s):

Parallel Processing ◽

Viterbi Decoder ◽

Processing Elements ◽

Decoder Architecture

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An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2018.2825362 ◽

2018 ◽

Vol 65 (10) ◽

pp. 3543-3554

Author(s):

N. Prasad ◽

Indrajit Chakrabarti ◽

Santanu Chattopadhyay

Keyword(s):

Energy Efficient ◽

Network On Chip ◽

Viterbi Decoder ◽

Decoder Architecture ◽

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An Efficient Viterbi Decoder Architecture

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-0234650 ◽

2013 ◽

Vol 2 (3) ◽

pp. 46-50

Author(s):

Kalpana. R Kalpana. R

Keyword(s):

Viterbi Decoder ◽

Decoder Architecture

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A low complexity soft-output Viterbi decoder architecture

Proceedings of ICC '93 - IEEE International Conference on Communications ◽

10.1109/icc.1993.397371 ◽

2002 ◽

Author(s):

C. Berrou ◽

P. Adde ◽

E. Angui ◽

S. Faudeil

Keyword(s):

Low Complexity ◽

Viterbi Decoder ◽

Decoder Architecture

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A new lower power Viterbi decoder architecture with glitch reduction

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) ◽

10.1109/apasic.1999.824034 ◽

2003 ◽

Author(s):

J.A. Ryu ◽

S.C. Kim ◽

J.D. Cho ◽

H.W. Park ◽

Y.H. Chang

Keyword(s):

Viterbi Decoder ◽

Lower Power ◽

Decoder Architecture ◽

Glitch Reduction

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Lower power Viterbi decoder architecture with a new clock-gating trace-back unit

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) ◽

10.1109/icvc.1999.820910 ◽

2003 ◽

Author(s):

Je Hyuk Ryu ◽

Sang Cheon Kim ◽

Jun Dong Cho ◽

Hyun Woo Park ◽

Yung Hoon Chang

Keyword(s):

Viterbi Decoder ◽

Clock Gating ◽

Lower Power ◽

Decoder Architecture

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A state-serial Viterbi decoder architecture for digital radio on FPGA

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005. ◽

10.1109/fpt.2005.1568582 ◽

2006 ◽

Author(s):

M. Petrov ◽

M. Glesner

Keyword(s):

Viterbi Decoder ◽

Digital Radio ◽

Decoder Architecture

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