Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

2007 ◽  
Vol 94 (10) ◽  
pp. 905-913 ◽  
Author(s):  
J. B. Kim ◽  
Y. S. Lee
2007 ◽  
Vol 43 (17) ◽  
pp. 911 ◽  
Author(s):  
A. Tajalli ◽  
E. Vittoz ◽  
Y. Leblebici ◽  
E.J. Brauer

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