Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

2006 ◽  
Vol 19 (5) ◽  
pp. S325-S330 ◽  
Author(s):  
Shuichi Nagasawa ◽  
Kenji Hinode ◽  
Tetsuro Satoh ◽  
Yoshihiro Kitagawa ◽  
Mutsuo Hidaka
Keyword(s):  
High Speed ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Flux Quantum ◽  
Access Memory ◽  
Cell Arrays

Nonvolatile Magnetoresistive Random-Access Memory Based on Magnetic Tunnel Junctions

MRS Bulletin ◽  
2004 ◽  
Vol 29 (11) ◽  
pp. 818-821 ◽  
Author(s):  
G. Grynkewich ◽  
J. Åkerman ◽  
P. Brown ◽  
B. Butcher ◽  
R.W. Dave ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Magnetoresistive Random Access Memory ◽  
Static Ram ◽  
New Memory Technology

AbstractMagnetoresistive random-access memory (MRAM) is a new memory technology that is nearing commercialization. MRAM integrates a magnetic tunnel junction (MTJ) device with standard silicon-based microelectronics, resulting in a combination of qualities not found in other memory technologies. For example, MRAM is nonvolatile, has unlimited read and write endurance, and is capable of high-speed read and write operations. In this article, we will describe the fundamentals of an MTJ-based MRAM as well as recent important technology developments in the areas of magnetic materials and memory cell architecture. In addition, we will compare the present and future capabilities of MRAM to those of existing memory technologies such as static RAM and flash memory.

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

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