The gyrator for transforming nano memristor into meminductor

Circuit World ◽  
2016 ◽  
Vol 42 (4) ◽  
pp. 197-200 ◽  
Author(s):  
Shao-Fu Wang

Purpose To solve the problem of meminductor in circuit design, this paper aims to describe a synthesis method and the mechanism in terms of constitutive relation of the gyrator for transforming nano memristor into meminductor. Design/methodology/approach The gyrator was designed to achieve memristor-meminductor transformation by using amplifiers and memristor. Findings The simulation results verify the flexibility of its operation. Originality/value This gyrator can be used in integrated circuit design such as filter, diplexer, and it has a simple and economical implementation.

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 215-219
Author(s):  
Akhendra Kumar Padavala ◽  
Narayana Kiran Akondi ◽  
Bheema Rao Nistala

Purpose This paper aims to present an efficient method to improve quality factor of printed fractal inductors based on electromagnetic band-gap (EBG) surface. Design/methodology/approach Hilbert fractal inductor is designed and simulated using high-frequency structural simulator. To improve the quality factor, an EBG surface underneath the inductor is incorporated without any degradation in inductance value. Findings The proposed inductor and Q factor are measured based on well-known three-dimensional simulator, and the results are compared experimentally. Practical implications The proposed method was able to significantly decrease the noise with increase in the speed of radio frequency and sensor-integrated circuit design. Originality/value Fractal inductor is designed and simulated with and without EBG surfaces. The measurement of printed circuit board prototypes demonstrates that the inclusion of split-ring array as EBG surface increases the quality factor by 90 per cent over standard fractal inductor of the same dimensions with a small degradation in inductance value and is capable of operating up to 2.4 GHz frequency range.


2014 ◽  
Vol 10 (3) ◽  
pp. 429-442
Author(s):  
Srinivas Sabbavarapu ◽  
Krunakar Reddy Basireddy ◽  
N. Srinivasulu ◽  
Amit Acharyya ◽  
Jimson Mathew

1986 ◽  
Vol 18 (9) ◽  
pp. 481-488 ◽  
Author(s):  
Brent E. Nelson ◽  
Darryl R. Morrell ◽  
Christopher J. Read ◽  
Kent F. Smith

Author(s):  
Hung-Sung Lin ◽  
Ying-Chin Hou ◽  
Juimei Fu ◽  
Mong-Sheng Wu ◽  
Vincent Huang ◽  
...  

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.


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