On the number of tests to detect all path delay faults in combinational logic circuits

IEEE Transactions on Computers ◽

10.1109/12.481486 ◽

1996 ◽

Vol 45 (1) ◽

pp. 50-62 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Logic Circuits ◽

Delay Faults ◽

Combinational Logic ◽

Path Delay Faults ◽

Combinational Logic Circuits

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Efficient diagnosis of path delay faults in digital logic circuits

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) ◽

10.1109/iccad.1999.810696 ◽

2003 ◽

Author(s):

P. Pant ◽

A. Chatterjee

Keyword(s):

Logic Circuits ◽

Digital Logic ◽

Delay Faults ◽

Path Delay Faults

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Synthesis of combinational logic circuits for path delay fault testability

10.1109/iscas.1990.112669 ◽

2002 ◽

Author(s):

A.K. Pramanick ◽

S.M. Reddy ◽

S. Sangupta

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Delay Fault ◽

Path Delay Fault ◽

Combinational Logic Circuits

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Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.953501 ◽

2001 ◽

Vol 9 (5) ◽

pp. 679-689 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Delay Fault ◽

Path Delay Fault ◽

Combinational Logic Circuits

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A Concurrent BIST Architecture for Combinational Logic Circuits

2020 10th International Conference on Computer and Knowledge Engineering (ICCKE) ◽

10.1109/iccke50421.2020.9303669 ◽

2020 ◽

Author(s):

Ahmad Menbari ◽

Hadi Jahanirad

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits

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Timing and Area Optimization of CMOS Combinational-Logic Circuits Accounting for Total-Dose Radiation Effects

IEEE Transactions on Nuclear Science ◽

10.1109/tns.1987.4337485 ◽

1987 ◽

Vol 34 (6) ◽

pp. 1386-1391 ◽

Author(s):

R. S. Gyurcsik ◽

D. W. Thomas ◽

R. H. Gallimore ◽

B. L. Bhuva ◽

S. E. Kerns

Keyword(s):

Radiation Effects ◽

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits ◽

Area Optimization ◽

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Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

IEEE Transactions on Computers ◽

10.1109/tc.1986.1676825 ◽

1986 ◽

Vol C-35 (8) ◽

pp. 742-754 ◽

Author(s):

Reddy ◽

Reddy

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits ◽

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Parallel pattern fault simulation of path delay faults

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89 ◽

10.1145/74382.74442 ◽

1989 ◽

Author(s):

M. Schulz ◽

F. Fink ◽

K. Fuchs

Keyword(s):

Fault Simulation ◽

Delay Faults ◽

Path Delay Faults ◽

Parallel Pattern

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On the design of fault diagnostic networks for combinational logic circuits

Microelectronics Reliability ◽

10.1016/0026-2714(75)90207-3 ◽

1975 ◽

Vol 14 (4) ◽

pp. 339

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits ◽

Fault Diagnostic

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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Fast test pattern generation for all path delay faults considering various test classes

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246529 ◽

2002 ◽

Author(s):

K. Fuchs ◽

H.C. Wittmann ◽

K.J. Antreich

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults

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