Stochastic verification of run-time performance adaptation with field delay testing

Author(s):  
Masanori Hashimoto
Author(s):  
Nattapong Kurpukdee ◽  
Phuttapong Sertsi ◽  
Sila Chunwijitra ◽  
Vataya Chunwijitra ◽  
Ananlada Chotimongkol ◽  
...  

2001 ◽  
Author(s):  
Georg Soumagne ◽  
Shinji Nagai ◽  
Naoto Hisanaga ◽  
Shinobu Nanzai ◽  
Yoshinori Ochiishi ◽  
...  

2006 ◽  
Vol 7 (S1) ◽  
pp. 151-158
Author(s):  
Xin Ji ◽  
Sofie Pollin ◽  
Gregory Lenoir ◽  
Gauthier Lafruit ◽  
Antoine Dejonghe ◽  
...  

2012 ◽  
Vol 22 (4-5) ◽  
pp. 574-613 ◽  
Author(s):  
MATTHEW NAYLOR ◽  
COLIN RUNCIMAN

AbstractA new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.


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