High-level synthesis scheduling and allocation using genetic algorithms

In this work we present a reconfigurable and scalable custom processor array for solving optimization problems using cellular genetic algorithms (cGAs), based on a regular fabric of processing nodes and local memories. Cellular genetic algorithms are a variant of the well-known genetic algorithm that can conveniently exploit the coarse-grain parallelism afforded by this architecture. To ease the design of the proposed computing engine for solving different optimization problems, a high-level synthesis design flow is proposed, where the problem-dependent operations of the algorithm are specified in C++ and synthesized to custom hardware. A spectrum allocation problem was used as a case study and successfully implemented in a Virtex-6 FPGA device, showing relevant figures for the computing acceleration.

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Genetic Algorithms for High-Level Synthesis in VLSI Design

Materials and Manufacturing Processes ◽

10.1081/amp-120022016 ◽

2003 ◽

Vol 18 (3) ◽

pp. 355-383 ◽

Cited By ~ 2

Author(s):

C. Mandal ◽

P. P. Chakrabarti

Keyword(s):

Genetic Algorithms ◽

Vlsi Design ◽

High Level Synthesis ◽

High Level

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A New Technique for the High-Level Synthesis of Digit-Serial Digital Filters Based on Genetic Algorithms

Journal of Circuits System and Computers ◽

10.1142/s0218126697000395 ◽

1997 ◽

Vol 07 (06) ◽

pp. 517-535 ◽

Cited By ~ 1

Author(s):

J. H. Satyanarayana ◽

B. Nowrouzian

Keyword(s):

Genetic Algorithms ◽

Digital Filter ◽

Optimization Technique ◽

High Level Synthesis ◽

Optimal Time ◽

Flow Graph ◽

Time Optimal ◽

Functional Units ◽

High Level ◽

The Cost

This paper is concerned with the exploitation of genetic algorithms and their application to the development of a new optimization technique for the high-level synthesis of digit-serial digital filter data-paths. In the resulting optimization technique, the cost associated with the final digital filter data-path is minimized subject to user-specified constraints on the number of physical arithmetic functional units employed. The proposed technique is capable of obtaining global area-optimal, time-optimal, or combined area-cum-time-optimal data-paths, where the optimality takes into account not only the cost associated with the required arithmetic functional units but also that associated with the required support cells (multiplexors and registers). This optimization is made computationally effective by encoding the digital filter data flow-graph into chromosomes which preserve the data-dependency relationships in the original digital filter signal flow-graph under the operations of crossover and mutation by the underlying genetic algorithm. The usefulness of the proposed technique is demonstrated by applying to the constrained optimization of a benchmark elliptic wave digital filter for full bit-serial, full bit-parallel, as well as general digit-serial high-level synthesis. The results thus obtained are compared to those of the existing techniques (whenever appropriate) to confirm the validity of the technique.

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