A 6.78-200 MHz Offset-Compensated Active Rectifier with Dynamic Logic Comparator for mm-size Wirelessly Powered Implants

Author(s):  
Jianming Zhao ◽  
Yuan Gao
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.


Author(s):  
Gokhan Ozkan ◽  
Phuong H. Hoang ◽  
Payam Ramezani Badr ◽  
Chris S. Edrington ◽  
Behnaz Papari

Author(s):  
Thomas Bolander ◽  
Thorsten Engesser ◽  
Andreas Herzig ◽  
Robert Mattmüller ◽  
Bernhard Nebel

2016 ◽  
Vol 31 (6) ◽  
pp. 4484-4498 ◽  
Author(s):  
Hyung-Gu Park ◽  
Jae-Hyeong Jang ◽  
Hong-Jin Kim ◽  
Young-Jun Park ◽  
SeongJin Oh ◽  
...  

1994 ◽  
Vol 41 (6) ◽  
pp. 2244-2251 ◽  
Author(s):  
D.J. Fouts ◽  
T. Weatherford ◽  
D. McMorrow ◽  
J.S. Melinger ◽  
A.B. Campbell

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