A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS

Author(s):  
Marc Pons ◽  
Christoph Thomas Muller ◽  
David Ruffieux ◽  
Jean-Luc Nagel ◽  
Stephane Emery ◽  
...  
Keyword(s):  
2010 ◽  
Vol 19 (07) ◽  
pp. 1449-1464 ◽  
Author(s):  
BYUNGHEE CHOI ◽  
YOUNGSOO SHIN

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.


2015 ◽  
Vol 51 (17) ◽  
pp. 1322-1324 ◽  
Author(s):  
Seung‐Tae Kim ◽  
Oh‐Kyong Kwon

2016 ◽  
Vol 64 ◽  
pp. 158-162 ◽  
Author(s):  
C. Ndiaye ◽  
V. Huard ◽  
X. Federspiel ◽  
F. Cacho ◽  
A. Bravaix
Keyword(s):  

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