Interturn voltage stress in electrical machine windings due to fast switching surges

1984 ◽  
Author(s):  
H. Oraee ◽  
P.G. McLaren
Keyword(s):  
Electrical Machine ◽  
Fast Switching ◽  
Voltage Stress

scholarly journals Method to Predict the Non-Uniform Potential Distribution in Random Electrical Machine Windings under Pulse Voltage Stress

Energies ◽  
2022 ◽  
Vol 15 (1) ◽  
pp. 358
Author(s):  
Alexander Hoffmann ◽  
Bernd Ponick
Keyword(s):  
Equivalent Circuit ◽  
Potential Distribution ◽  
Solution Process ◽  
Practical Method ◽  
Electrical Machine ◽  
Stator Core ◽  
Design Data ◽  
Potential Oscillations ◽  
Voltage Stress ◽  
The Time Domain

This article describes a practical method for predicting the distribution of electric potential inside an electrical machine’s winding based on design data. It broadens the understanding of winding impedance in terms of inter-winding behavior and allows to properly design an electrical machine’s insulation system during the development phase. The predictions are made based on an frequency-dependent equivalent circuit of the electrical machine which is validated by measurements in the time domain and the frequency domain. Element parameters for the equivalent circuit are derived from two-dimensional field simulations. The results demonstrate a non-uniform potential distribution and demonstrate that the potential difference between individual turns and between turns and the stator core exceeds the expected values. The findings also show a link between winding impedance and potential oscillations inside the winding. Additionally, the article provides an overview of the chronological progression of turn-based models and shows how asynchronous multiprocessing is used to accelerate the solution process of the equivalent circuit.

New Holtz Electrical Machine

1877 ◽  
Vol 3 (70supp) ◽  
pp. 1108-1108
Author(s):  
Elihu Thomson
Keyword(s):  
Electrical Machine

Iron Loss Characteristics of Motors Fed by Fast Switching GaN-FET Inverters

2020 ◽  
Vol 140 (6) ◽  
pp. 488-494
Author(s):  
Haruo Naitoh ◽  
Takaya Sugimoto ◽  
Keisuke Fujisaki
Keyword(s):  
Iron Loss ◽  
Fast Switching ◽  
Gan Fet

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Methodology for Analysis of Schottky Diode Failures

2010 ◽  
Author(s):  
Bhanu P. Sood ◽  
Michael Pecht ◽  
John Miker ◽  
Tom Wanek
Keyword(s):  
Failure Mode ◽  
Schottky Diode ◽  
Failure Modes ◽  
Schottky Diodes ◽  
Failure Mechanisms ◽  
Forward Voltage ◽  
Fast Switching ◽  
Voltage Drops ◽  
The Common

Abstract Schottky diodes are semiconductor switching devices with low forward voltage drops and very fast switching speeds. This paper provides an overview of the common failure modes in Schottky diodes and corresponding failure mechanisms associated with each failure mode. Results of material level evaluation on diodes and packages as well as manufacturing and assembly processes are analyzed to identify a set of possible failure sites with associated failure modes, mechanisms, and causes. A case study is then presented to illustrate the application of a systematic FMMEA methodology to the analysis of a specific failure in a Schottky diode package.

Analysis of Induced End-of-Life Failures in SRAM Through Nanoprobing

2018 ◽  
Author(s):  
Oberon Dixon-Luinenburg ◽  
Jordan Fine
Keyword(s):  
End Of Life ◽  
Soft Errors ◽  
Cause Analysis ◽  
New Approach ◽  
Performance Loss ◽  
Root Cause ◽  
Long Period ◽  
Atomic Force ◽  
Stress Resultant ◽  
Voltage Stress

Abstract In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.

High-Density Memristor-CMOS Ternary Logic Family

2020 ◽  
Author(s):  
Xiaoyuan Wang ◽  
Pengfei Zhou ◽  
Jason Eshraghian ◽  
Chih-Yang Lin ◽  
Herbert Ho-Ching Iu ◽  
...  
Keyword(s):  
Indium Tin Oxide ◽  
Practical Implementation ◽  
Switching Speed ◽  
High Data ◽  
Fast Switching ◽  
Data Density ◽  
Order Of Magnitude ◽  
High Transconductance ◽  
Logic Functions ◽  
Magnitude Improvement

<div>This paper presents the first experimental demonstration</div><div>of a ternary memristor-CMOS logic family. We systematically</div><div>design, simulate and experimentally verify the primitive</div><div>logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.</div>

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