Standard cell library and automated design flow for circuits on flexible substrates

2009 ◽  
Author(s):  
Shrinivas Gopalan Uppili ◽  
David R. Allee ◽  
Sameer M. Venugopal ◽  
Lawrence T. Clark ◽  
Rahul Shringarpure
Keyword(s):  
Automated Design ◽  
Design Flow ◽  
Flexible Substrates ◽  
Standard Cell ◽  
Standard Cell Library ◽  
Cell Library

Superconductor Standard Cell Library for Advanced EDA Design Flow

2021 ◽  
pp. 1-1
Author(s):  
Sukanya Sagarika Meher ◽  
Jushya Ravi ◽  
Mustafa Eren Celik ◽  
Stephen Miller ◽  
Anubhav Sahu ◽  
...  
Keyword(s):  
Design Flow ◽  
Standard Cell ◽  
Standard Cell Library ◽  
Cell Library

Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library

2018 ◽  
Vol 34 (6) ◽  
pp. 735-747 ◽  
Author(s):  
Pablo Ilha Vaz ◽  
Thiago Hanna Both ◽  
Fábio Fedrizzi Vidor ◽  
Raphael Martins Brum ◽  
Gilson Inácio Wirth
Keyword(s):  
Design Flow ◽  
Standard Cell ◽  
Standard Cell Library ◽  
Cell Library ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

NMLib: A Nanomagnetic Logic Standard Cell Library

2021 ◽  
Author(s):  
Laysson Oliveira Luz ◽  
Jose Augusto M. Nacif ◽  
Ricardo S. Ferreira ◽  
Omar P. Vilela Neto
Keyword(s):  
Standard Cell ◽  
Standard Cell Library ◽  
Nanomagnetic Logic ◽  
Cell Library

scholarly journals Countermeasures against Static Power Attacks

2021 ◽  
pp. 780-805
Author(s):  
Thorben Moos ◽  
Amir Moradi
Keyword(s):  
Process Variations ◽  
Cost Effective ◽  
Design Flow ◽  
Sensitive Information ◽  
Standard Cell ◽  
Aging Effects ◽  
Cell Library ◽  
Effective Option ◽  
Static Power ◽  
Power Attacks

In recent years it has been demonstrated convincingly that the standby power of a CMOS chip reveals information about the internally stored and processed data. Thus, for adversaries who seek to extract secrets from cryptographic devices via side-channel analysis, the static power has become an attractive quantity to obtain. Most works have focused on the destructive side of this subject by demonstrating attacks. In this work, we examine potential solutions to protect circuits from silently leaking sensitive information during idle times. We focus on countermeasures that can be implemented using any common digital standard cell library and do not consider solutions that require full-custom or analog design flow. In particular, we evaluate and compare a set of five distinct standard-cell-based hiding countermeasures, including both, randomization and equalization techniques. We then combine the hiding countermeasures with state-of-the-art hardware masking in order to amplify the noise level and achieve a high resistance against attacks. An important part of our contribution is the proposal and evaluation of the first ever standard-cell-based balancing scheme which achieves perfect data-independence on paper, i.e., in absence of intra-die process variations and aging effects. We call our new countermeasure Exhaustive Logic Balancing (ELB). While this scheme, applied to a threshold implementation, provides the highest level of resistance in our experiments, it may not be the most cost effective option due to the significant resource overhead associated. All evaluated countermeasures and combinations thereof are applied to a serialized hardware implementation of the PRESENT block cipher and realized as cryptographic co-processors on a 28nm CMOS ASIC prototype. Our experimental results are obtained through real-silicon measurements of a fabricated die of the ASIC in a temperature-controlled environment using a source measure unit (SMU). We believe that our elaborate comparison serves as a useful guideline for hardware designers to find a proper tradeoff between security and cost for almost any application.

Sign in / Sign up

Export Citation Format

Share Document