Stochastic flash ADC considering comparator metastability implemented in FPGA

2017 ◽  
Author(s):  
Astria Nur Irfansyah ◽  
Hendra Kusuma
Keyword(s):  
Flash Adc

A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process

2009 ◽  
Vol E92-C (2) ◽  
pp. 258-268 ◽  
Author(s):  
Ying-Zu LIN ◽  
Soon-Jyh CHANG ◽  
Yen-Ting LIU
Keyword(s):  
Cmos Process ◽  
Flash Adc

A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC

2020 ◽  
Author(s):  
Nitish Kumar ◽  
R. K. Siddharth ◽  
Y.B. Nithin Kumar ◽  
M.H Vasantha
Keyword(s):  
Flash Adc ◽  
Multi Level

Flash ADC‐based digital LDO with non‐linear decoder and exponential‐ratio array

2019 ◽  
Vol 55 (10) ◽  
pp. 585-587 ◽  
Author(s):  
Zhendong Ding ◽  
Xinyu Xu ◽  
Haixin Song ◽  
Woogeun Rhee ◽  
Zhihua Wang
Keyword(s):  
Flash Adc ◽  
Non Linear

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

Parallel processing of flash-ADC data for the jet-chamber of jade

1988 ◽  
Vol 263 (1) ◽  
pp. 206-211 ◽  
Author(s):  
G. Eckerlin ◽  
E. Elsen ◽  
H.v.d. Schmitt ◽  
A. Wagner ◽  
P.v. Walter ◽  
...  
Keyword(s):  
Parallel Processing ◽  
Flash Adc

Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product

2015 ◽  
Vol 23 (8) ◽  
pp. 1518-1527 ◽  
Author(s):  
James Lin ◽  
Ibuki Mano ◽  
Masaya Miyahara ◽  
Akira Matsuzawa
Keyword(s):  
High Speed ◽  
Design Strategy ◽  
Flash Adc

A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

2013 ◽  
Vol 77 (2) ◽  
pp. 285-289 ◽  
Author(s):  
Guanzhong Huang ◽  
Pingfen Lin
Keyword(s):  
Time Domain ◽  
Flash Adc
Sign in / Sign up

Export Citation Format

Share Document