Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers

Proceedings of ICC '93 - IEEE International Conference on Communications ◽

10.1109/icc.1993.397239 ◽

2002 ◽

Author(s):

G. Caire ◽

J. Ventura-Traveset ◽

M. Hollreiser ◽

E. Biglieri

Keyword(s):

Vlsi Implementation ◽

Systolic Architecture

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Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1007/bf02407033 ◽

1995 ◽

Vol 10 (2) ◽

pp. 153-168

Author(s):

G. Caire ◽

J. Ventura-Traveset ◽

M. Hollreiser ◽

E. Biglieri

Keyword(s):

Vlsi Implementation ◽

Systolic Architecture

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

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Very high speed real-time IIR digital filter structures: suitable for VLSI implementation

1993 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.1993.393798 ◽

2002 ◽

Author(s):

K.K. Dhar

Keyword(s):

Real Time ◽

Digital Filter ◽

Vlsi Implementation ◽

Filter Structures ◽

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A systolic architecture for high speed hypergraph partitioning using a genetic algorithm

Progress in Evolutionary Computation - Lecture Notes in Computer Science ◽

10.1007/3-540-60154-6_51 ◽

1995 ◽

pp. 109-126 ◽

Author(s):

Heming Chan ◽

Pinaki Mazumder

Keyword(s):

Genetic Algorithm ◽

Systolic Architecture ◽

Hypergraph Partitioning

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A Static-Reconfigurable Systolic Architecture using Barrel Shifters for High Speed Digital Signal Processing

10.1109/milcom.1986.4805735 ◽

1986 ◽

Author(s):

P. A. Ramamoorthy ◽

T. Chen

Keyword(s):

Signal Processing ◽

Digital Signal Processing ◽

Digital Signal ◽

Systolic Architecture

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Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme

Journal of Signal Processing Systems ◽

10.1007/s11265-009-0437-1 ◽

2009 ◽

Vol 61 (2) ◽

pp. 219-230

Author(s):

Peng Cao ◽

Chao Wang ◽

Long X. Shi

Keyword(s):

Wavelet Transform ◽

Discrete Wavelet Transform ◽

Lifting Scheme ◽

Vlsi Implementation ◽

Discrete Wavelet ◽

Two Dimensional ◽

Memory Efficient

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A novel ortho normalized multi-stage discrete fast Stockwell transform based memory-aware high-speed VLSI implementation for image compression

Multimedia Tools and Applications ◽

10.1007/s11042-018-7055-5 ◽

2019 ◽

Vol 78 (13) ◽

pp. 17673-17699 ◽

Author(s):

G kiranmaye ◽

Srinivasulu Tadisetty

Keyword(s):

Image Compression ◽

Vlsi Implementation ◽

Multi Stage ◽

Stockwell Transform

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A VLSI implementation of an interface for a dual protocol high speed active bus

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1992.271107 ◽

2003 ◽

Author(s):

S. Ng ◽

J.V. Peursem ◽

M. Hassoun ◽

J. Davis ◽

A. Pohm

Keyword(s):

Vlsi Implementation

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VLSI implementation of a high-speed and low-power punctured Viterbi decoder

2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings. ◽

10.1109/tencon.2002.1180342 ◽

2003 ◽

Author(s):

Li Qiao ◽

You Yuxin ◽

Wang Jinxiang ◽

Ye Yizheng

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Viterbi Decoder

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A systolic architecture for high speed pipelined memories

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93 ◽

10.1109/iccd.1993.393343 ◽

2002 ◽

Author(s):

A.G. Dickinson ◽

C.J. Nicol

Keyword(s):

Systolic Architecture

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