Satisfiability based test generation for stuck-at fault coverage in RTL circuits using VHDL

The testability distribution of a VLSI circuit is modeled as a series of step functions over the interval [0, 1]. The model generalizes previous related work on testability. Unlike previous work, however, we include estimates of testability by random vectors. Quadratic programming methods are used to estimate the parameters of the testability distribution from fault coverage data (random and deterministic) on a sample of faults. The estimated testability is then used to predict the random and deterministic fault coverage distributions without the need to employ test generation or fault simulations. The prediction of fault coverage distribution can answer important questions about the “goodness” of a design from a testing point of view. Experimental results are given on the large ISCAS-85 and ISCAS-89 circuits.

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Mixed level test generation for high fault coverage

Microprocessing and Microprogramming ◽

10.1016/0165-6074(91)90438-y ◽

1991 ◽

Vol 32 (1-5) ◽

pp. 791-796 ◽

Cited By ~ 3

Author(s):

U. Hübner ◽

H. Hinsen ◽

M. Hofebauer ◽

H.T. Vierhaus

Keyword(s):

Test Generation ◽

Fault Coverage

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Horizontal diversity in test generation for high fault coverage

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES ◽

10.3906/elk-1805-212 ◽

2018 ◽

Vol 26 (6) ◽

pp. 3259-3274 ◽

Cited By ~ 2

Author(s):

Arbab ALAMGIR ◽

Abu Khari Bin A’AIN ◽

Norlina PARAMAN ◽

Usman Ullah SHEIKH ◽

Ian GROUT

Keyword(s):

Test Generation ◽

Fault Coverage

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On-chip Generation of Functional Tests with Reduced Delay and Power

Bulletin of Electrical Engineering and Informatics ◽

10.11591/eei.v6i1.570 ◽

2017 ◽

Vol 6 (1) ◽

pp. 36-46

Author(s):

Hemanth Kumar Motamarri ◽

B. Leela Kumari

Keyword(s):

Test Generation ◽

Fault Coverage ◽

Pattern Generation ◽

Functional Tests ◽

Primary Input ◽

Transition Fault ◽

High Transition ◽

On Chip

This paper describes different methods on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.

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