Timing verification and optimization for the PowerPC processor family

2002 ◽  
Author(s):  
R.E. Mains ◽  
T.A. Mosher ◽  
L.P.P.P. van Ginneken ◽  
R.F. Damiano
Keyword(s):  
Timing Verification

Timing verification of component-based vehicle software with rubus-ICE

2018 ◽  
Author(s):  
Saad Mubeen ◽  
Mattias Gålnander ◽  
Alessio Bucaioni ◽  
John Lundbäck ◽  
Kurt-Lennart Lundbäck
Keyword(s):  
Timing Verification

Timing Verification

2009 ◽  
pp. 227-316 ◽  
Author(s):  
J. Bhasker ◽  
Rakesh Chadha
Keyword(s):  
Timing Verification

scholarly journals An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 580
Author(s):  
Peng Cao ◽  
Wei Bao ◽  
Jingjing Guo
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Timing Analysis ◽  
Instruction Set ◽  
Timing Verification ◽  
Static Timing Analysis ◽  
Static Timing ◽  
Threshold Voltages ◽  
Layer Stacking ◽  
Reduced Instruction Set Computer

The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods.

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