A high-speed real-time digital pulse compression system based on TMS320C6201

Pulse compression technology is one of the key technologies in the field of modern radar signal processing, can effectively solve the contradiction between action distance and resolution. In this paper, a radar digital pulse compression system is designed and implemented based on FPGA with linear frequency modulated signal. The digital pulse compression module is designed using FFT IP core which can be reused in different periods of DPC, respectively performing FFT and IFFT calculation, so that the hardware consumption is saved significantly. Therefore, compared with other systems, the system designed in this paper has the characters of fast processing speed, high degree of modularity, real-time processing and short development cycle.

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Design of Frequence and Angle Measurement System Based on FFT and Monbit Receiver

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.236-237.923 ◽

2012 ◽

Vol 236-237 ◽

pp. 923-928

Author(s):

Xiu Qing Zhang ◽

Guo Chen An ◽

Xiao Jun Wang

Keyword(s):

High Speed ◽

Pulse Compression ◽

Design Method ◽

Complex Multiplication ◽

Angle Measurement ◽

Low Power Consumption ◽

Matlab Simulation ◽

Digital Pulse ◽

Xilinx Fpga ◽

Logic Resource

In this paper, a design method of high-speed, real-time digital pulse compression module based on Xilinx FPGA devices and Monbit receiver is introduced. A novel changeable-points of 256 or 1024 for three channels Digital Pulse Compression(DPC) with realizing FFT , complex-multiplication and IFFT function are presented which is accomplished by FPGA. A top-down flow has been used in the system. The whole design, which characters high stability, small logic resource occupation, low power consumption, is implemented with only one chip of FPGA XC2V500-5 for one channel. It takes 73.31us to complete a 1024-point DPC. Compared with the MATLAB simulation results, our module can accomplish function of 32k points digital pulse compression of 200MSPS throughput.

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Microcomputer-based digital pulse compression system for ultrasonic NDT

Ultrasonics ◽

10.1016/0041-624x(87)90024-2 ◽

1987 ◽

Vol 25 (3) ◽

pp. 166-171 ◽

Cited By ~ 8

Author(s):

F.K. Lam

Keyword(s):

Pulse Compression ◽

Compression System ◽

Digital Pulse ◽

Ultrasonic Ndt

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High Real-Time Design of Digital Pulse Compression Based on FPGA

Mathematical Problems in Engineering ◽

10.1155/2015/792862 ◽

2015 ◽

Vol 2015 ◽

pp. 1-7 ◽

Cited By ~ 4

Author(s):

Xiujie Qu ◽

Cuimei Ma ◽

Shixin Zhang ◽

Sitong Lian

Keyword(s):

Real Time ◽

Processing Speed ◽

Pulse Compression ◽

Fourier Transforms ◽

Experimental Result ◽

Parallel Structure ◽

Time Performance ◽

Fft Processor ◽

Digital Pulse ◽

Floating Point Computation

Because of the poor real-time performance of in-place fast Fourier transforms, a reconfigurable radix-4 FFT processor is studied and designed, which is based on decimation-in-time and single floating-point computation. The proposed method adopts “pipeline and parallel” structure for accessing multiple memories to improve the FFT processing speed, and then it is applied to digital pulse compression. The experimental result shows that the proposed FFT based on radix-4 computation can implement digital pulse compression rapidly under no adding hardware resources. The proposed method can be also applied to other radix FFTs.

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Design of High Speed and Parallel Compression System Used in the Big Area CCD of High Frame Frequency

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.411.488 ◽

2011 ◽

Vol 411 ◽

pp. 488-496

Author(s):

Yan Yan Liu ◽

Yin Han Gao ◽

Guo Ning Li ◽

Wen Hua Wang ◽

Ran Feng Zhang ◽

...

Keyword(s):

Image Compression ◽

Real Time ◽

High Speed ◽

Analog Signal ◽

Compression Scheme ◽

Compression System ◽

Real Time Image ◽

Integration Degree ◽

Time Image ◽

Frame Frequency

According to the area CCD camera of characteristics, such as high resolution capacity and high frame frequency, this paper puts forward a high speed and parallel image compression system of high integration degree. Firstly, according to the work principle of the area CCD, FPGA is adopted to realize the timing driving and multichannel and parallel analog signal handling to raise the export frame frequency of the area CCD. Secondly, with an image compression scheme based on FPGA embedded processor MicroBlaze and ADV212 compression chip, real time image compression and the high speed area CCD are realized. Finally, by detecting the analog signal of the area CCD output, the real time compression of the big area CCD image is carried out in different compression ratios and the compression performance is analyzed. Experiment result shows that this scheme can realize real time image compression with the biggest data rate of 520Mbps. When compression bit ratio is 0.15, the signal-to-noise ratio of peak value can reach 36 dB. Image collection and image compression are integrated, which reduces the data transmission between them and improves systematic integration degree.

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