A 5.6-mW power dissipation CMOS frequency synthesizer for L1/L2 dual-band GPS application

Author(s):  
Hailong Jia ◽  
Tong Ren ◽  
Min Lin ◽  
Fangxiong Chen ◽  
Yin Shi ◽  
...  
2018 ◽  
Vol 27 (08) ◽  
pp. 1850131 ◽  
Author(s):  
Mostafa Azadbakht ◽  
Ali Sahafi ◽  
Esmaeil Najafi Aghdam

This work presents a fully integrated fractional-[Formula: see text] frequency synthesizer that covers the entire frequency bands specified in the IEEE 802.11 a/b/g/n. In this paper, the effects of charge pump (CP) gain mismatch on spectral purity of local oscillator signal is studied theoretically and a new high precision self-calibrated CP is presented for alleviating the nonidealities. The idea is implemented in a 0.18-[Formula: see text]m standard CMOS technology. According to post layout simulation, the proposed calibration circuit demonstrates an excellent matching in the CP currents in a wide voltage range. By using this technique, the average of close-in phase noise of the designed frequency synthesizer is suppressed by more than 12[Formula: see text]dBc. The active whole chip die area is 0.475[Formula: see text]mm2 and the power dissipation from a 1.8-V DC supply is 17.3–20.6[Formula: see text]mW.


2004 ◽  
Vol 39 (1) ◽  
pp. 234-237 ◽  
Author(s):  
W.-Z. Chen ◽  
J.-X. Chang ◽  
Y.-J. Hong ◽  
M.-T. Wong ◽  
C.-L. Kuo

Author(s):  
Yu-Kai Tsai ◽  
Yi-Keng Hsieh ◽  
Hung-Yu Tsai ◽  
Huan-Sheng Chen ◽  
Liang-Hung Lu

Sign in / Sign up

Export Citation Format

Share Document