Si (100)-GaN/Si (111) low temperature wafer bonding process for 3D power supply on chip

2019 ◽  
Author(s):  
Ryuki Ishito ◽  
Kota Ono ◽  
Satoshi Matsumoto
Keyword(s):  
Low Temperature ◽  
Power Supply ◽  
Wafer Bonding ◽  
Bonding Process ◽  
On Chip

TLP Bonding Technologies for Micro Joining and 3D Packaging

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001221-001252 ◽  
Author(s):  
Kei Murayama ◽  
Mitsuhiro Aizawa ◽  
Mitsutoshi Higashi
Keyword(s):  
High Temperature ◽  
Melting Point ◽  
Low Temperature ◽  
Wafer Bonding ◽  
Bonding Process ◽  
Tlp Bonding ◽  
Hermetic Sealing ◽  
Low Temperature Bonding ◽  
Free Material ◽  
Bonding Technique

The bonding technique for High density Flip Chip(F.C.) packages requires a low temperature and a low stress process to have high reliability of the micro joining ,especially that for sensor MEMS packages requires hermetic sealing so as to ensure their performance. The Transient Liquid Phase (TLP) bonding, that is a kind of diffusion bonding is a technique that connects the low melting point material such as Indium to the higher melting point metal such as Gold by the isothermal solidification and high-melting-point intermetallic compounds are formed. Therefore, it is a unique joining technique that can achieve not only the low temperature bonding and also the high temperature reliability. The Gold-Indium TLP bonding technique can join parts at 180 degree C and after bonding the melting point of the junction is shifted to more than 495 degree C, therefore itfs possible to apply the low temperature bonding lower than the general use as a lead free material such as a SAC and raise the melting point more than AuSn solder which is used for the high temperature reliability usage. Therefore, the heat stress caused by bonding process can be expected to be lowered. We examined wafer bonding and F.C bonding plus annealing technique by using electroplated Indium and Gold as a joint material. We confirmed that the shear strength obtained at the F.C. bonding plus anneal technique was equal with that of the wafer bonding process. Moreover, it was confirmed to ensure sufficient hermetic sealing in silicon cavity packages that had been bonded at 180 degree C. And the difference of the thermal stress that affect to the device by the bonding process was confirmed. In this paper, we report on various possible application of the TLP bonding.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Novel low-temperature CMOS-compatible full-wafer-bonding process for the fabrication of 3D embedded microchannels using SU-8

2004 ◽  
Author(s):  
Francisco J. Blanco ◽  
Maria Agirregabiria ◽  
Maria Tijero ◽  
Javier Berganzo ◽  
Jorge Garcia ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Bonding Process ◽  
Cmos Compatible

Low Temperature O2 Plasma-Assisted Wafer Bonding of InP and a Garnet Crystal for an Optical Waveguide Isolator

2007 ◽  
Vol 124-126 ◽  
pp. 475-478 ◽  
Author(s):  
J.W. Roh ◽  
J.S. Yang ◽  
S.H. Ok ◽  
Deok Ha Woo ◽  
Young Tae Byun ◽  
...  
Keyword(s):  
Low Temperature ◽  
Optical Waveguide ◽  
Wafer Bonding ◽  
Bonding Process ◽  
Garnet Crystal ◽  
Integrated Optical ◽  
Temperature Heat ◽  
Integrated Optical Waveguide ◽  
Temperature Heat Treatment ◽  
O2 Plasma

A novel process of wafer bonding between InP and a garnet crystal (Gd3Ga5O12, CeY2Fe5O12) based on O2 plasma surface-activation and low temperature heat treatment is presented. The O2 plasma assisted wafer bonding process was found to be very effective in bonding of InP and Gd3Ga5O12, providing good bonding strength and hydrophilicity as well as no voids in the interface, which is crucial for fabrication of an integrated optical waveguide isolator. The isolation ratio of an integrated optical waveguide isolator fabricated by the O2 plasma assisted wafer bonding process was obtained to be 2.9 dB.

A versatile and flexible low-temperature full-wafer bonding process of monolithic 3D microfluidic structures in SU-8

2008 ◽  
Vol 18 (9) ◽  
pp. 095013 ◽  
Author(s):  
J Steigert ◽  
O Brett ◽  
C Müller ◽  
M Strasser ◽  
N Wangler ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Bonding Process

scholarly journals Photonic Integration on the Hybrid Silicon Evanescent Device Platform

2008 ◽  
Vol 2008 ◽  
pp. 1-17 ◽  
Author(s):  
Hyundai Park ◽  
Alexander W. Fang ◽  
Di Liang ◽  
Ying-Hao Kuo ◽  
Hsu-Hao Chang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Wafer Bonding ◽  
Optical Gain ◽  
Hybrid Structure ◽  
Bonding Process ◽  
Wafer Level ◽  
Device Structure ◽  
Silicon Waveguides ◽  
Hybrid Silicon

This paper reviews the recent progress of hybrid silicon evanescent devices. The hybrid silicon evanescent device structure consists of III-V epitaxial layers transferred to silicon waveguides through a low-temperature wafer bonding process to achieve optical gain, absorption, and modulation efficiently on a silicon photonics platform. The low-temperature wafer bonding process enables fusion of two different material systems without degradation of material quality and is scalable to wafer-level bonding. Lasers, amplifiers, photodetectors, and modulators have been demonstrated with this hybrid structure and integration of these individual components for improved optical functionality is also presented. This approach provides a unique way to build photonic active devices on silicon and should allow application of silicon photonic integrated circuits to optical telecommunication and optical interconnects.

Effect of nanoscale surface topography on low temperature direct wafer bonding process with UV activation

2009 ◽  
Vol 151 (1) ◽  
pp. 81-86 ◽  
Author(s):  
Zirong Tang ◽  
Ping Peng ◽  
Tielin Shi ◽  
Guanglan Liao ◽  
Lei Nie ◽  
...  
Keyword(s):  
Low Temperature ◽  
Surface Topography ◽  
Wafer Bonding ◽  
Bonding Process ◽  
Direct Wafer Bonding

A Simple Technique for Sub-10 nm Planar Nanofluidic Channel Fabrication

2009 ◽  
Vol 1222 ◽  
Author(s):  
Chunrong Song ◽  
Pingshan Wang
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Silicon Surface ◽  
Etch Rate ◽  
Simple Technique ◽  
Low Voltage ◽  
Low Cost ◽  
Bonding Process ◽  
Native Oxide ◽  
Nanofluidic Channels

AbstractA simple and low-cost technique is demonstrated to fabricate sub-10 nm planar nanofluidic channels. Native oxide on silicon surface is etched with a multiple hydrofluoric (HF)-etch / SiO2-regrowth process. Shallow Si trenches with 3 nm to 24 nm depths are obtained at an etch rate of 1 nm per HF dip. The trenches are uniform with a surface r.m.s. roughness of 0.4 - 0.6 nm. A low-temperature and low-voltage anodic wafer bonding process is then used to form planar nanofluidic channels. Minimum aspect ratio (depth/width) of the fabricated sub-10 nm nanochannels is around 0.001-0.002.

Analytical methods used for low temperature Cu–Cu wafer bonding process evaluation

2015 ◽  
Vol 21 (5) ◽  
pp. 1003-1013 ◽  
Author(s):  
B. Rebhan ◽  
S. Tollabimazraehno ◽  
G. Hesser ◽  
V. Dragoi
Keyword(s):  
Low Temperature ◽  
Process Evaluation ◽  
Wafer Bonding ◽  
Analytical Methods ◽  
Bonding Process
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