A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

2008 ◽  
Author(s):  
C.-H. Jan ◽  
P. Bai ◽  
S. Biswas ◽  
M. Buehler ◽  
Z.-P. Chen ◽  
...  
Keyword(s):  
Power System ◽  
Low Power ◽  
System On Chip ◽  
Metal Gate ◽  
Chip Technology ◽  
High K ◽  
Silicon Transistors ◽  
Low Power System ◽  
Dual Gate ◽  
On Chip

Low-power system-on-chip architecture for wireless LANs

2004 ◽  
Vol 151 (1) ◽  
pp. 2 ◽  
Author(s):  
L. Bisdounis ◽  
C. Dre ◽  
S. Blionas ◽  
D. Metafas ◽  
A. Tatsaki ◽  
...  
Keyword(s):  
Power System ◽  
Low Power ◽  
Wireless Lans ◽  
System On Chip ◽  
Low Power System ◽  
On Chip

Adaptive circuit block model for power supply noise analysis of low power system-on-chip

2009 ◽  
Author(s):  
Matthias Eireiner ◽  
Doris Schmitt-Landsiedel ◽  
Paul Wallner ◽  
Andreas Schone ◽  
Stephan Henzler ◽  
...  
Keyword(s):  
Power System ◽  
Low Power ◽  
Power Supply ◽  
Noise Analysis ◽  
System On Chip ◽  
Block Model ◽  
Supply Noise ◽  
Low Power System ◽  
Adaptive Circuit ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document