Iterator-Based Optimization of Imperfectly-Nested Loops

Topology and computational-power aware tile mapping of perfectly nested loops with dependencies on distributed systems

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2019.03.002 ◽

2019 ◽

Vol 129 ◽

pp. 14-35 ◽

Cited By ~ 1

Author(s):

Ebrahim Zarei Zefreh ◽

Shahriar Lotfi ◽

Leyli Mohammad Khanli ◽

Jaber Karimpour

Keyword(s):

Distributed Systems ◽

Computational Power ◽

Nested Loops ◽

Tile Mapping

Download Full-text

TRANSFORMATION OF NESTED LOOPS WITH MODULO INDEXING TO AFFINE RECURRENCES

Parallel Processing Letters ◽

10.1142/s0129626494000260 ◽

1994 ◽

Vol 04 (03) ◽

pp. 271-280 ◽

Cited By ~ 6

Author(s):

FLORIN BALASA ◽

FRANK H.M. FRANSSEN ◽

FRANCKY V.M. CATTHOOR ◽

HUGO J. DE MAN

Keyword(s):

Code Generation ◽

State Of The Art ◽

Transformation Method ◽

Control Flow ◽

Code Optimization ◽

Transformation Techniques ◽

Hermite Normal Form ◽

Nested Loops ◽

Affine Functions ◽

Systems Transformation

For multi-dimensional (M-D) signal and data processing systems, transformation of algorithmic specifications is a major instrument both in code optimization and code generation for parallelizing compilers and in control flow optimization as a preprocessor for architecture synthesis. State-of-the-art transformation techniques are limited to affine index expressions. This is however not sufficient for many important applications in image, speech and numerical processing. In this paper, a novel transformation method is introduced, oriented to the subclass of algorithm specifications that contains modulo expressions of affine functions to index M-D signals. The method employs extensively the concept of Hermite normal form. The transformation method can be carried out in polynomial time, applying only integer arithmetic.

Download Full-text

Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling

Parallel Processing Letters ◽

10.1142/s0129626497000383 ◽

1997 ◽

Vol 07 (04) ◽

pp. 379-392 ◽

Cited By ~ 20

Author(s):

Alain Darte ◽

Georges-André Silber ◽

Frédéric Vivien

Keyword(s):

Dependence Graph ◽

Loop Tiling ◽

Loop Parallelization ◽

Fine Grain ◽

Loop Body ◽

Nested Loops ◽

Single Block ◽

The Way

Tiling is a technique used for exploiting medium-grain parallelism in nested loops. It relies on a first step that detects sets of permutable nested loops. All algorithms developed so far consider the statements of the loop body as a single block, in other words, they are not able to take advantage of the structure of dependences between different statements. In this paper, we overcame this limitation by showing how the structure of the reduced dependence graph can be taken into account for detecting more permutable loops. Our method combines graph retiming techniques and graph scheduling techniques. It can be viewed as an extension of Wolf and Lam's algorithm to the case of loops with multiple statements. Loan independent dependences play a particular role in our study, and we show how the way we handle them can be useful for fine-grain loop parallelization as well.

Download Full-text