The Failure Mechansim of the E-SOA Boundary of Power Transistor Collapsed at Higher Gate Voltage

Author(s):  
Jian-Hsing Lee ◽  
Karuna Nidhi ◽  
Tingyou Lin ◽  
Hsueh-Chun Liao ◽  
Fu-Chun Tseng ◽  
...  
Author(s):  
Arkadiusz Glowacki ◽  
Christian Boit ◽  
Richard Lossy ◽  
Joachim Würfl

Abstract Non-degraded and degraded AlGaN/GaN HEMT devices have been characterized electrically and investigated in various operating modes using integral and spectrally resolved photon emission (PE). In degraded devices the PE dependence on the gate voltage differs from the non-degraded devices. Various types of dependencies on the gate voltage have been identified when investigating local degradation sites. PE spectroscopy was performed at various bias conditions. For both devices broad spectra have been obtained in a wavelength regime from visible to near-infrared, including local performance variations. Signatures of the degradation have been determined in the electrical characterization, in integral PE distribution and in the PE spectrum.


1989 ◽  
Vol 25 (15) ◽  
pp. 979 ◽  
Author(s):  
A.P. Long ◽  
I.H. Goodridge ◽  
J.P. King ◽  
A.J. Holden ◽  
J.G. Metcalfe ◽  
...  
Keyword(s):  

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 330
Author(s):  
Georges Pananakakis ◽  
Gérard Ghibaudo ◽  
Sorin Cristoloveanu

Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle-like. In this case, the metamorphosis is accentuated by smaller size, lower doping, and higher gate voltage. After defining the geometrical criterion for square-to-circle shift, simulation results are used to document the main consequences. This transition occurs naturally in nanowires thinner than 50 nm. The results are rather universal, and supportive evidence is gathered from inversion-mode Gate-All-Around (GAA) MOSFETs as well as from thermal diffusion process.


Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 63
Author(s):  
Saima Hasan ◽  
Abbas Z. Kouzani ◽  
M A Parvez Mahmud

This paper presents a simple and comprehensive model of a dual-gate graphene field effect transistor (FET). The quantum capacitance and surface potential dependence on the top-gate-to-source voltage were studied for monolayer and bilayer graphene channel by using equivalent circuit modeling. Additionally, the closed-form analytical equations for the drain current and drain-to-source voltage dependence on the drain current were investigated. The distribution of drain current with voltages in three regions (triode, unipolar saturation, and ambipolar) was plotted. The modeling results exhibited better output characteristics, transfer function, and transconductance behavior for GFET compared to FETs. The transconductance estimation as a function of gate voltage for different drain-to-source voltages depicted a proportional relationship; however, with the increase of gate voltage this value tended to decline. In the case of transit frequency response, a decrease in channel length resulted in an increase in transit frequency. The threshold voltage dependence on back-gate-source voltage for different dielectrics demonstrated an inverse relationship between the two. The analytical expressions and their implementation through graphical representation for a bilayer graphene channel will be extended to a multilayer channel in the future to improve the device performance.


Author(s):  
Jie Ma ◽  
Long Zhang ◽  
Jing Zhu ◽  
Wangming Cui ◽  
Weifeng Sun ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.


Author(s):  
Mengjun Du ◽  
Jinfeng Zhao ◽  
Dongli Zhang ◽  
Huaisheng Wang ◽  
Qi Shan ◽  
...  

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