Optimum design for a two-stage CMOS I/O ESD protection circuit

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) ◽

10.1109/iscas.1998.706854 ◽

2002 ◽

Author(s):

Tong Li ◽

P. Bendix ◽

D. Suh ◽

Y.J. Huh ◽

E. Rosenbaum ◽

...

Keyword(s):

Optimum Design ◽

Two Stage ◽

Esd Protection ◽

Protection Circuit

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Design of All-Directional ESD Protection circuit with SCR-based I/O and LIGBT-based Power clamp

2021 International Conference on Electronics, Information, and Communication (ICEIC) ◽

10.1109/iceic51217.2021.9369761 ◽

2021 ◽

Author(s):

Kyoung-Il Do ◽

Seung-Hoo Jin ◽

Byung-Seok Lee ◽

Je-Wook Woo ◽

Yong-Seo Koo

Keyword(s):

Esd Protection ◽

Protection Circuit

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An ESD protection circuit for SOI technology using gate- and body-biased MOSFETs

IEEE International SOI Conference SOI-02 ◽

10.1109/soi.2002.1044410 ◽

2002 ◽

Author(s):

Salman ◽

Mitra ◽

Ioannou ◽

Fechner ◽

Liu

Keyword(s):

Esd Protection ◽

Protection Circuit ◽

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BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit

2010 11th International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2010.5450396 ◽

2010 ◽

Author(s):

Ming-Ta Yang ◽

Yang Du ◽

Charles Teng ◽

Tony Chang ◽

Eugene Worley ◽

...

Keyword(s):

Esd Protection ◽

Protection Circuit

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The Design of LVDS Transmitter with ESD Protection Circuit using BiCMOS Technologies

2007 International Symposium on Signals, Circuits and Systems ◽

10.1109/isscs.2007.4292648 ◽

2007 ◽

Author(s):

Yong-Seo Koo ◽

Jo-Woon Lee ◽

Jae-Hyun Lee ◽

Kwang-Yeob Lee ◽

Jae-Chang Kwak ◽

...

Keyword(s):

Esd Protection ◽

Protection Circuit

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Design of high-reliability LDO with current limiting characteristics with built-in new high tolerance ESD protection circuit

IEICE Electronics Express ◽

10.1587/elex.10.20130516 ◽

2013 ◽

Vol 10 (20) ◽

pp. 20130516-20130516

Author(s):

Jin Woo Jung ◽

Yong Seo Koo ◽

Kwang Yeob Lee

Keyword(s):

High Reliability ◽

High Tolerance ◽

Current Limiting ◽

Esd Protection ◽

Protection Circuit

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Layout and Technology Influences on ESD Protection Circuit Design

On-Chip ESD Protection for Integrated Circuits - The International Series in Engineering and Computer Science ◽

10.1007/0-306-47618-5_7 ◽

2006 ◽

pp. 171-218

Keyword(s):

Circuit Design ◽

Esd Protection ◽

Protection Circuit

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Substrate-triggered ESD protection circuit without extra process modification

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.807168 ◽

2003 ◽

Vol 38 (2) ◽

pp. 295-302 ◽

Author(s):

Ming-Dou Ker ◽

Tung-Yang Chen

Keyword(s):

Process Modification ◽

Esd Protection ◽

Protection Circuit

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Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

IEEE Transactions on Electron Devices ◽

10.1109/ted.2019.2954754 ◽

2020 ◽

Vol 67 (1) ◽

pp. 40-46

Author(s):

Rong-Kun Chang ◽

Ming-Dou Ker

Keyword(s):

High Voltage ◽

Low Voltage ◽

Negative Voltage ◽

Esd Protection ◽

Protection Circuit ◽

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A package method for reducing bus crosstalk in full chip ESD protection circuit

2010 11th International Conference on Electronic Packaging Technology & High Density Packaging ◽

10.1109/icept.2010.5582758 ◽

2010 ◽

Author(s):

Zhang Bing ◽

Chai Chang-chun ◽

Yang Yin-Tang

Keyword(s):

Esd Protection ◽

Protection Circuit

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ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology

2009 IEEE Custom Integrated Circuits Conference ◽

10.1109/cicc.2009.5280729 ◽

2009 ◽

Author(s):

H. Sarbishaei ◽

M. Sachdev

Keyword(s):

Cmos Technology ◽

Esd Protection ◽

Protection Circuit

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