Noise coupling to signal trace and via from power/ground simultaneous switching noise in high speed double data rates memory module

The paper studies a simultaneous switching noise (SSN) in a power distribution network (PDN) with dual supply voltages and two cores. This is achieved by reducing the admittance matrix Y of the PDN then calculating frequency domain impedance with rational function approximation using vector fitting. This paper presents a method of computing the simultaneous switching noise through a switching current, whose properties and details are described. Thus, the results are discussed and performed using MATLAB and PSpice tools. It demonstrated that the presence of many cores in the same PCB influences the SSN due to electromagnetic coupling.

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SIMULTANEOUS SWITCHING NOISE ANALYSIS OF A 16 MB × 9 DRAM SIMM MEMORY MODULE

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156495000249 ◽

1995 ◽

Vol 06 (04) ◽

pp. 647-668

Author(s):

JONG-HOON PARK ◽

HONG-JUNE PARK ◽

BO-KYOUNG CHOI ◽

OH-HYUN KIM ◽

SI-DON CHOI

Keyword(s):

Noise Analysis ◽

Circuit Model ◽

Switching Noise ◽

Memory Module ◽

Simultaneous Switching Noise ◽

Sense Amplifiers ◽

Simultaneous Switching ◽

Parameter Values ◽

Simulation Time ◽

Good Agreement

HSPICE simulations have been performed for a 16 Mb×9 SIMM memory module and the simultaneous switching noise has been investigated. The SPICE model of the SIMM memory module is made up of a PCB circuit model and a simplified DRAM chip model. To keep the SPICE simulation time within reasonable bounds, a simplified circuit model of a 16 Mb DRAM chip was generated by keeping the basic physical DRAM structure in the model including the bit-line sense amplifiers. The parameter values of the circuit elements in the simplified DRAM chip model were tuned to fit the measured transient supply current waveform of a commercial 16 Mb DRAM chip. The SIMM module was placed on a fabricated motherboard PCB and the simultaneous switching noise voltage on the motherboard VSS plane was measured. Good agreement between measurements and HSPICE simulations were observed.

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A NOVEL DESIGN METHODOLOGY FOR REDUCING SIMULTANEOUS SWITCHING NOISE EVALUATED BY A DIFFERENTIAL-IBIS STRUCTURE

Journal of Circuits System and Computers ◽

10.1142/s0218126610006670 ◽

2010 ◽

Vol 19 (06) ◽

pp. 1275-1297

Author(s):

WEN-TZENG HUANG ◽

SUN-YEN TAN ◽

YUAN-JEN CHANG

Keyword(s):

Integrated Circuit ◽

High Speed ◽

Low Voltage ◽

Switching Noise ◽

Decoupling Capacitors ◽

Input Noise ◽

Low Voltage Operation ◽

Simultaneous Switching Noise ◽

Simultaneous Switching ◽

Ibis Model

Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.

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