On-chip Interconnect Optimization and Validation using Virtual Platform

2020 ◽  
Author(s):  
Jungyun Choi ◽  
Kyungsu Kang ◽  
Sangho Park ◽  
Seunghan Lee ◽  
Yohan Park ◽  
...  
Keyword(s):  
Interconnect Optimization ◽  
Virtual Platform ◽  
On Chip

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support

2013 ◽  
Author(s):  
Dexue Zhang ◽  
Xiaoyang Zeng ◽  
Zongyan Wang ◽  
Weike Wang ◽  
Xinhua Chen
Keyword(s):  
Networks On Chip ◽  
Virtual Platform ◽  
On Chip ◽  
Many Core

Virtual Verification and Validation of Automotive System

2019 ◽  
Vol 28 (04) ◽  
pp. 1950071
Author(s):  
Mona Safar ◽  
Magdy A. El-Moursy ◽  
Mohamed Abdelsalam ◽  
Ayman Bakr ◽  
Keroles Khalil ◽  
...  
Keyword(s):  
Fault Injection ◽  
Electronic Control Unit ◽  
Control Unit ◽  
Verification And Validation ◽  
System Level ◽  
Development Cycle ◽  
Virtual Platform ◽  
On Chip ◽  
Automotive System

An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.

scholarly journals Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft-Core Processor

2020 ◽  
Vol 2020 ◽  
pp. 1-7
Author(s):  
Zineb El Hariti ◽  
Abdelhakim Alali ◽  
Mohamed Sadik ◽  
Kaoutar Aamali
Keyword(s):  
High Performance ◽  
System Level ◽  
Limiting Factor ◽  
Power Budget ◽  
Technology Roadmap ◽  
Systems On Chip ◽  
Limited Power ◽  
Virtual Platform ◽  
On Chip ◽  
Technology Nodes

Nowadays, modern embedded applications are becoming more and more complex and resource demanding. Fortunately, Systems on Chip (SoC) are one of the keys used to follow their requirements that stand in need of high performance while maintaining a low-power profile. On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. To address this challenge, designing at the system level is the suitable measure to tackle with the complexity of the Systems on Chip, aiming at having better adjustment between timing and accuracy for power and temperature estimations. We present in this paper, at the first stage, two models describing the static and dynamic power at the physical level. These models are implemented on an open virtual platform Model Power-Consumption and Temperature in SystemC/TLM (LIBTLMPWT) based on a representative SoC architecture. At the second stage, we focus on power, especially the thermal behaviour of the chip while running three benchmarks set on the game of life application for two different technology nodes.

scholarly journals Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level

2021 ◽  
Author(s):  
Quentin Forcioli ◽  
Jean-Luc Danger ◽  
Clementine Maurice ◽  
Lilian Bossuet ◽  
Florent Bruguier ◽  
...  
Keyword(s):  
System On Chip ◽  
Virtual Platform ◽  
On Chip

Gut microbiome a promising target for management of respiratory diseases

2020 ◽  
Vol 477 (14) ◽  
pp. 2679-2696
Author(s):  
Riddhi Trivedi ◽  
Kalyani Barve
Keyword(s):  
Respiratory Diseases ◽  
New Technology ◽  
Bacterial Flora ◽  
Systemic Circulation ◽  
The Body ◽  
Lung Pathology ◽  
Promising Target ◽  
Current Therapies ◽  
Intestinal Microbial Flora ◽  
On Chip

The intestinal microbial flora has risen to be one of the important etiological factors in the development of diseases like colorectal cancer, obesity, diabetes, inflammatory bowel disease, anxiety and Parkinson's. The emergence of the association between bacterial flora and lungs led to the discovery of the gut–lung axis. Dysbiosis of several species of colonic bacteria such as Firmicutes and Bacteroidetes and transfer of these bacteria from gut to lungs via lymphatic and systemic circulation are associated with several respiratory diseases such as lung cancer, asthma, tuberculosis, cystic fibrosis, etc. Current therapies for dysbiosis include use of probiotics, prebiotics and synbiotics to restore the balance between various species of beneficial bacteria. Various approaches like nanotechnology and microencapsulation have been explored to increase the permeability and viability of probiotics in the body. The need of the day is comprehensive study of mechanisms behind dysbiosis, translocation of microbiota from gut to lung through various channels and new technology for evaluating treatment to correct this dysbiosis which in turn can be used to manage various respiratory diseases. Microfluidics and organ on chip model are emerging technologies that can satisfy these needs. This review gives an overview of colonic commensals in lung pathology and novel systems that help in alleviating symptoms of lung diseases. We have also hypothesized new models to help in understanding bacterial pathways involved in the gut–lung axis as well as act as a futuristic approach in finding treatment of respiratory diseases caused by dysbiosis.

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