27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS

2016 ◽  
Author(s):  
Jiangfeng Wu ◽  
Acer Chou ◽  
Tianwei Li ◽  
Rong Wu ◽  
Tao Wang ◽  
...  
Keyword(s):  
Pipelined Adc

A 7.21-bit ENOB 100MS/s 1.51mW Inverter based Pipelined ADC with Digital Calibration for Breast Cancer Detection System

2020 ◽  
Vol 140 (6) ◽  
pp. 585-591
Author(s):  
Yoshihiro Masui ◽  
Tsukasa Nishimiya ◽  
Allex Uemi ◽  
Akihiro Toya ◽  
Takamaro Kikkawa
Keyword(s):  
Breast Cancer ◽  
Cancer Detection ◽  
Detection System ◽  
Breast Cancer Detection ◽  
Digital Calibration ◽  
Pipelined Adc

Digital Background Calibration for a 14-bit 100-MS/s Pipelined ADC Using Signal-Dependent Dithering

2014 ◽  
Vol E97.C (3) ◽  
pp. 207-214
Author(s):  
Zhao-xin XIONG ◽  
Min CAI ◽  
Xiao-Yong HE ◽  
Yun YANG
Keyword(s):  
Pipelined Adc ◽  
Background Calibration ◽  
Digital Background Calibration

VLSI DESIGN OF PIPELINED ADC WITH WIDE RANGE OPERATING TEMPERATURE FOR WAVE APPLICATIONS

2017 ◽  
Vol 6 (2) ◽  
pp. 13
Author(s):  
P LOKESH ◽  
U. SOMALATHA ◽  
S. CHANDANA ◽  
◽  
◽  
...  
Keyword(s):  
Operating Temperature ◽  
Vlsi Design ◽  
Pipelined Adc ◽  
Wide Range

scholarly journals Digital Error Correction Logic for Pipelined ADC Using 1.5Bits/Stage

2020 ◽  
Vol 981 ◽  
pp. 032046
Author(s):  
Y. Srikanth ◽  
Ch. Rajendra Prasad ◽  
Koteshwar Rao Danthamala ◽  
P. Ramchandar Rao ◽  
A. Chakradhar
Keyword(s):  
Error Correction ◽  
Pipelined Adc

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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