An analytical delay model for CMOS Inverter-Transmission Gate structure

2014 ◽  
Author(s):  
Mohammad Shueb Romi ◽  
Naushad Alam ◽  
M. Yusuf Yasin
Keyword(s):  
Delay Model ◽  
Cmos Inverter ◽  
Transmission Gate ◽  
Gate Structure ◽  
Analytical Delay Model

scholarly journals Analytical delay model of CMOS inverter including channel-length modulation

1992 ◽  
Vol 28 (4) ◽  
pp. 408 ◽  
Author(s):  
H.-C. Chow ◽  
W.-S. Feng
Keyword(s):  
Channel Length ◽  
Delay Model ◽  
Cmos Inverter ◽  
Analytical Delay Model

CMOS Inverter Degradation Delay Model

2005 ◽  
pp. 75-126
Author(s):  
Jorge Juan Chico ◽  
Alejandro Millán Calderón
Keyword(s):  
Delay Model ◽  
Cmos Inverter

scholarly journals Network Delays and Link Capacities in Application-Specific Wormhole NoCs

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-15 ◽  
Author(s):  
Zvika Guz ◽  
Isask'har Walter ◽  
Evgeny Bolotin ◽  
Israel Cidon ◽  
Ran Ginosar ◽  
...  
Keyword(s):  
Interconnection Networks ◽  
Packet Delay ◽  
Capacity Allocation ◽  
Delay Model ◽  
Capacity Assignment ◽  
Systems On Chip ◽  
Individual Capacity ◽  
On Chip ◽  
Analytical Delay Model ◽  
Application Specific

Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.

scholarly journals Improving Analytical Delay Modelingfor CMOS Inverters

2015 ◽  
Vol 10 (2) ◽  
pp. 123-134
Author(s):  
Felipe S. Marranghello ◽  
André I. Reis ◽  
Renato P. Ribas
Keyword(s):  
Integrated Circuits ◽  
Timing Analysis ◽  
Channel Length ◽  
Delay Model ◽  
Digital Integrated Circuits ◽  
Cmos Inverter ◽  
Worst Case ◽  
Average Value ◽  
Coupling Capacitance ◽  
Novel Approach

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

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