Low-noise wide dynamic range readout circuit for multi-stage microfluidic cell sorting systems

Designing low-noise current readout circuits at high speed is challenging. There is a need for preamplification stages to amplify weak input currents before being processed by conventional integrator based readout. However, the high current gain preamplification stage usually limits the dynamic range. This article presents a 140 dB input dynamic range low-noise current readout circuit with a noise floor of 10 fArms/sq(Hz). The architecture uses a programmable bidirectional input current gain stage followed by an integrator-based analog-to-pulse conversion stage. The programmable current gains setting enables one to achieve higher overall input dynamic range. The readout circuit is designed and in 0.18 μm CMOS and consumes 10.3 mW power from a 1.8 V supply. The circuit has been verified using post-layout simulations.

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A readout circuit with wide dynamic range for differential capacitive sensing applications

2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) ◽

10.1109/ccece.2013.6567799 ◽

2013 ◽

Cited By ~ 1

Author(s):

Fatemeh Aezinia ◽

Behraad Bahreyni

Keyword(s):

Dynamic Range ◽

Readout Circuit ◽

Capacitive Sensing ◽

Wide Dynamic Range ◽

Sensing Applications

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A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126618501049 ◽

2018 ◽

Vol 27 (07) ◽

pp. 1850104 ◽

Cited By ~ 2

Author(s):

Yuwadee Sundarasaradula ◽

Apinunt Thanachayanont

Keyword(s):

Low Power ◽

Biomedical Applications ◽

Dynamic Range ◽

Supply Voltage ◽

Low Noise ◽

Power Supply Voltage ◽

Wide Dynamic Range ◽

Dc Offset ◽

Limiting Amplifier ◽

Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

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