Low-Power, High-Sensitivity Readout Integrated Circuit With Clock-Gating, Double-Edge-Triggered Flip-Flop for Mid-Wavelength Infrared Focal-Plane Arrays

2019 ◽  
Vol 3 (9) ◽  
pp. 1-4 ◽  
Author(s):  
Chi Yeon Kim ◽  
Hee Chul Lee
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Focal Plane ◽  
High Sensitivity ◽  
Focal Plane Arrays ◽  
Clock Gating ◽  
Infrared Focal Plane Arrays ◽  
Readout Integrated Circuit ◽  
Flip Flop ◽  
Double Edge

320×256 Readout Integrated Circuit for Infrared Focal Plane Arrays with Low-temperature MOSFET Model

2011 ◽  
Vol 57 (6) ◽  
pp. 550 ◽  
Author(s):  
Weifeng Sun ◽  
Kan Jia ◽  
Qingsong Qian ◽  
Liang Xie ◽  
Yangfan Zhou ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Focal Plane ◽  
Focal Plane Arrays ◽  
Infrared Focal Plane Arrays ◽  
Readout Integrated Circuit

scholarly journals DESIGN OF READOUT INTEGRATED CIRCUIT FOR UNCOOLED INFRARED FOCAL PLANE ARRAYS BASED ON MICROCANTILEVER

2010 ◽  
Vol 29 (2) ◽  
pp. 97-101 ◽  
Author(s):  
Jun-Min CAO ◽  
Zhong-Jian CHEN ◽  
Wen-Gao LU ◽  
Ya-Cong ZHANG ◽  
Ke LEI ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Focal Plane ◽  
Focal Plane Arrays ◽  
Infrared Focal Plane Arrays ◽  
Readout Integrated Circuit

Dependence of the Deformation of 128×128 InSb Focal-plane Arrays on the Silicon Readout Integrated Circuit Thickness

2015 ◽  
Vol 9 (1) ◽  
pp. 170-174 ◽  
Author(s):  
Xiaoling Zhang ◽  
Qingduan Meng ◽  
Liwen Zhang
Keyword(s):  
Thermal Shock ◽  
Indium Antimonide ◽  
Integrated Circuit ◽  
Focal Plane ◽  
Three Dimensional ◽  
Fracture Probability ◽  
Focal Plane Arrays ◽  
Thermal Shock Test ◽  
Readout Integrated Circuit ◽  
Three Dimensional Modeling

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.

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