High performance decoupled control of wound-rotor induction motor using matrix method and digital signal processor

2005 ◽  
Author(s):  
Y. Kawabata ◽  
E. Ejiogu ◽  
T. Kawabata
Keyword(s):  
Induction Motor ◽  
Digital Signal Processor ◽  
Matrix Method ◽  
High Performance ◽  
Digital Signal ◽  
Decoupled Control ◽  
Signal Processor

Design and Implementation of Low Power and Area Efficient Architecture for High Performance ALU

2021 ◽  
Author(s):  
Usthulamuri Penchalaiah ◽  
V. G. Siva Kumar
Keyword(s):  
Digital Signal Processor ◽  
High Performance ◽  
Architectural Design ◽  
Digital Signal ◽  
Building Blocks ◽  
Delay Performance ◽  
Art Research ◽  
Comparative Results ◽  
Almost All ◽  
Signal Processor

Digital Signal Processors (DSP) have a ubiquitous presence in almost all civil and military signal processing applications, including mission critical environments like nuclear reactors, process control etc. Arithmetic and Logic units (ALU), being the heart of any digital signal processor, play critical and decisive roles in achieving the required parameter benchmarks and the overall efficiency and robustness of the digital signal processor. State of the art research has shown successful traction with the performance requirements of critical Multiply-Accumulate (MAC) parameters, like reduced power consumption, small electronic real estate footprint and reduction in delay with the associated design complexity. Judicious placement of its building blocks, namely, the truncated multiplier and half-sum carry generation-sum carry generation (HSCG-SCG) adder in the architectural design of ALU and the type of adder and multiplier circuits selected are the core decisions that decide the overall performance of the ALU. To overcome the drawback and to improve the performance further, this work proposes a new architecture for the square root (SQRT) carry select adder (CSLA) using half-sum generation (HSG), half-carry generation (HCG), full-sum generation (FSG) and full-carry generation (FCG) blocks. The proposed design contains N-bit architecture, and comparative results are considered for 8-bit, 16-bit and 32-bit combinations. All the designs are implemented in the Xilinx ISE environment and the results show that better area, power, and delay performance compared to the state of art methods.

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