Frequency Multiplier-by-4 (Quadrupler) with 52 dB Spurious-Free Dynamic Range for 152 GHz to 220 GHz (G-Band) in 130 nm SiGe

2020 ◽  
Author(s):  
Paul Starke ◽  
Vincent Ries ◽  
Corrado Carta ◽  
Frank Ellinger
Keyword(s):  
Dynamic Range ◽  
Frequency Multiplier ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

Large Spurious-free Dynamic Range RoF Link with Tunable CSR

2021 ◽  
Author(s):  
Ruiqiong Wang ◽  
Yangyu Fan ◽  
Jiajun Tan ◽  
Yongsheng Gao
Keyword(s):  
Dynamic Range ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

2013 ◽  
Vol 473 ◽  
pp. 50-53
Author(s):  
Jie Lin ◽  
Fei Yan Mu
Keyword(s):  
Dynamic Range ◽  
Harmonic Distortion ◽  
High Accuracy ◽  
Pipeline Adc ◽  
Nonlinearity Error ◽  
Front End ◽  
Sample And Hold ◽  
Spurious Free Dynamic Range ◽  
Bicmos Process ◽  
Free Dynamic

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.

A photonic transmission link with enhanced dynamic range by incorporating phase shifters in dual drive dual parallel Mach–Zehnder modulator

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Sarika Singh ◽  
Sandeep K. Arya ◽  
Shelly Singla ◽  
Pulkit Berwal
Keyword(s):  
Dynamic Range ◽  
Control Method ◽  
Phase Shifters ◽  
Optical Modulator ◽  
Rf Signals ◽  
Single Sideband Modulation ◽  
Spurious Free Dynamic Range ◽  
Optical Single Sideband ◽  
Mach Zehnder Modulator ◽  
Free Dynamic

Abstract A linearization scheme is proposed for microwave photonic link to enlarge spurious free dynamic range using a dual-electrode dual parallel Mach–Zehnder modulator (MZM). This scheme employs phase control method to improve performance of the link by adjusting phase of radio frequency (RF) signals and bias voltages of optical modulator. Optical single sideband modulation is achieved through sub-modulators of dual parallel MZM which increases efficiency of the link. The simulated results show that third order intermodulation distortion is suppressed by 28 dB when the input RF signals are 9.1 and 9.5 GHz and noise floor is at −161 dBm/Hz. The spurious free dynamic range is also improved by 12.6 dB.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

Two-Dimensional Structure Compatible with DEM Methods Utilizing in DACs

2018 ◽  
Vol 27 (09) ◽  
pp. 1850142 ◽  
Author(s):  
Mehdi Bandali ◽  
Omid Hashemipour
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Dimensional Structure ◽  
Signal Frequency ◽  
Two Dimensional ◽  
Dynamic Element Matching ◽  
Digital To Analog Converter ◽  
Spurious Free Dynamic Range ◽  
Analog Converter ◽  
Free Dynamic

A two-dimensional digital-to-analog converter (DAC) structure compatible with dynamic element matching (DEM) methods is presented. Unlike the DACs using segmented structure for employing DEM, the new structure randomizes inter-segment error. This advantage is achieved because of the characteristics of the algorithm of two-dimensional decoding. The simulation results in 180[Formula: see text]nm CMOS technology, 319.72[Formula: see text]MHz signal frequency and 800[Formula: see text]MS/s sample rate for an 8-bit two-dimensional DAC utilizing the presented structure, shows 14.94[Formula: see text]dB spurious-free dynamic range (SFDR) improvement compared to the SFDR of the same DAC without employing the presented structure. Also, the IMD3 of the DAC employing the presented structure for [Formula: see text][Formula: see text]MHz and [Formula: see text][Formula: see text]MHz is 50.1[Formula: see text]dB.

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