HCFTL: A Locality-Aware Flash Translation Layer for Efficient Address Translation

Author(s):  
Yubiao Pan ◽  
Hao Chen ◽  
Jianing Zhao ◽  
Yinlong Xu
2020 ◽  
Vol 66 (3) ◽  
pp. 242-250 ◽  
Author(s):  
Yubiao Pan ◽  
Yongkun Li ◽  
Huizhen Zhang ◽  
Hao Chen ◽  
Mingwei Lin

2014 ◽  
Vol 49 (4) ◽  
pp. 743-758 ◽  
Author(s):  
Bharath Pichai ◽  
Lisa Hsu ◽  
Abhishek Bhattacharjee

2014 ◽  
Vol 42 (1) ◽  
pp. 743-758 ◽  
Author(s):  
Bharath Pichai ◽  
Lisa Hsu ◽  
Abhishek Bhattacharjee

2013 ◽  
Vol 464 ◽  
pp. 365-368 ◽  
Author(s):  
Ji Jun Hung ◽  
Kai Bu ◽  
Zhao Lin Sun ◽  
Jie Tao Diao ◽  
Jian Bin Liu

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.


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