A Data Skew Oriented Reduce Placement Algorithm Based on Sampling

2020 ◽  
Vol 8 (4) ◽  
pp. 1149-1161 ◽  
Author(s):  
Zhuo Tang ◽  
Wen Ma ◽  
Kenli Li ◽  
Keqin Li
2020 ◽  
Vol 14 (1) ◽  
pp. 69-81
Author(s):  
C.H. Li ◽  
Q.W. Yang

Background: Structural damage identification is a very important subject in the field of civil, mechanical and aerospace engineering according to recent patents. Optimal sensor placement is one of the key problems to be solved in structural damage identification. Methods: This paper presents a simple and convenient algorithm for optimizing sensor locations for structural damage identification. Unlike other algorithms found in the published papers, the optimization procedure of sensor placement is divided into two stages. The first stage is to determine the key parts in the whole structure by their contribution to the global flexibility perturbation. The second stage is to place sensors on the nodes associated with those key parts for monitoring possible damage more efficiently. With the sensor locations determined by the proposed optimization process, structural damage can be readily identified by using the incomplete modes yielded from these optimized sensor measurements. In addition, an Improved Ridge Estimate (IRE) technique is proposed in this study to effectively resist the data errors due to modal truncation and measurement noise. Two truss structures and a frame structure are used as examples to demonstrate the feasibility and efficiency of the presented algorithm. Results: From the numerical results, structural damages can be successfully detected by the proposed method using the partial modes yielded by the optimal measurement with 5% noise level. Conclusion: It has been shown that the proposed method is simple to implement and effective for structural damage identification.


Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1399
Author(s):  
Taepyeong Kim ◽  
Sangun Park ◽  
Yongbeom Cho

In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.


Author(s):  
Asmaa M. Hafez ◽  
Amany Abdelsamea ◽  
Ali A. El-Moursy ◽  
Salwa M. Nassar ◽  
Magda Bahaa ElDin Fayek

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 423
Author(s):  
Márk Szalay ◽  
Péter Mátray ◽  
László Toka

The stateless cloud-native design improves the elasticity and reliability of applications running in the cloud. The design decouples the life-cycle of application states from that of application instances; states are written to and read from cloud databases, and deployed close to the application code to ensure low latency bounds on state access. However, the scalability of applications brings the well-known limitations of distributed databases, in which the states are stored. In this paper, we propose a full-fledged state layer that supports the stateless cloud application design. In order to minimize the inter-host communication due to state externalization, we propose, on the one hand, a system design jointly with a data placement algorithm that places functions’ states across the hosts of a data center. On the other hand, we design a dynamic replication module that decides the proper number of copies for each state to ensure a sweet spot in short state-access time and low network traffic. We evaluate the proposed methods across realistic scenarios. We show that our solution yields state-access delays close to the optimal, and ensures fast replica placement decisions in large-scale settings.


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