A Fully Differential Rail-to-Rail CMOS Capacitance Sensor With Floating-Gate Trimming for Mismatch Compensation

2009 ◽  
Vol 56 (5) ◽  
pp. 975-986 ◽  
Author(s):  
S.B. Prakash ◽  
P. Abshire
2011 ◽  
Vol 58 (7) ◽  
pp. 1604-1614 ◽  
Author(s):  
Jose Maria Algueta Miguel ◽  
Antonio J. Lopez-Martin ◽  
Lucia Acosta ◽  
Jaime Ramirez-Angulo ◽  
Ramón Gonzalez Carvajal
Keyword(s):  

Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).


1990 ◽  
Vol 25 (1) ◽  
pp. 173-183 ◽  
Author(s):  
R.K. Hester ◽  
K.-S. Tan ◽  
M. de Wit ◽  
J.W. Fattaruso ◽  
S. Kiriaki ◽  
...  

Author(s):  
Thawatchai Thongleam ◽  
Apirak Suadet ◽  
Arnon Kanjanop ◽  
Pratchayaporn Singhanath ◽  
Buncha Hirunsing ◽  
...  

2010 ◽  
Vol 97-101 ◽  
pp. 3765-3768
Author(s):  
Shih Han Lin ◽  
Shu Jung Chen ◽  
Chih Hsiung Shen

A new modified CMOS buffer amplifier with rail-to-rail input and output range is proposed by TSMC 0.35μm 2P4M process at 3.3V supply. The technique adds dummy pairs to sense the common mode range of the input differential pair and adjusts the output current accordingly. The amplifier provides high gain for a wider range of output voltages. Design considerations for reducing the impact of the additional circuitry on the core are provided. The technique described can be adapted for use with traditional fully-differential rail-to-rail amplifiers, which performs 86.9dB ~92dB dc gain, 15 MHz unit-gain bandwidth, high driving ability with high slew rate under a 100pF capacitance and a 3kΩ series resistance loading. The simulation results indicate that the settling times of rising and falling edge are within 3.5μs. It is effective for a high resolution and high speed LCD driver.


Author(s):  
Giuseppe Ferri ◽  
Vincenzo Stornelli ◽  
Andrea De Marcellis ◽  
Angelo Celeste

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