scholarly journals Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

2010 ◽  
Vol 57 (1) ◽  
pp. 72-82 ◽  
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M.V. Krishna ◽  
Manh Anh Do ◽  
Kiat Seng Yeo ◽  
Chirn Chye Boon ◽  
Wei Meng Lim
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scholarly journals Design of Ultra Low Power 7.2 GHz True Single Phase Clock CMOS 2/3 Prescaler244 µW

IJARCCE ◽  
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Roshan Kumar ◽  
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Keyword(s):  
Low Power ◽  
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Ultra Low Power ◽  
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Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

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Kleber Stangherlin ◽  
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scholarly journals Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

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Vol 54 (2) ◽  
pp. 550-559 ◽  
Author(s):  
Yunpeng Cai ◽  
Anand Savanth ◽  
Pranay Prabhat ◽  
James Myers ◽  
Alex S. Weddell ◽  
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Low Power ◽  
Single Phase ◽  
Flip Flop ◽  
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scholarly journals A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

2017 ◽  
Vol 14 (8) ◽  
pp. 20170065-20170065
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Xincun Ji ◽  
Xiaojuan Xia ◽  
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Keyword(s):  
Low Power ◽  
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scholarly journals A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

2017 ◽  
Vol 14 (1) ◽  
pp. 20160446-20160446 ◽  
Author(s):  
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Qinjin Huang
Keyword(s):  
Low Power ◽  
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A Single-Phase Energy Metering SoC with IAS-DSP and Ultra Low Power Metering Mode

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Yan Zhao ◽  
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Kun Yang ◽  
Changyou Men ◽  
Nianxiong Nick Tan ◽  
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Keyword(s):  
Low Power ◽  
Single Phase ◽  
Ultra Low Power ◽  
Energy Metering ◽  
Power Metering
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