Dynamic Range Analysis in High Efficiency Video Coding Residual Coding and Reconstruction

2013 ◽  
Vol 23 (7) ◽  
pp. 1131-1136 ◽  
Author(s):  
Chuohao Yeo ◽  
Yih Han Tan ◽  
Zhengguo Li
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Dynamic Range ◽  
High Efficiency Video Coding ◽  
Range Analysis ◽  
Residual Coding

High-Performance Hardware Interpolation Architecture for High Efficiency Video Coding Decoder

2016 ◽  
Vol 11 (9) ◽  
pp. 764
Author(s):  
Lella Aicha Ayadi ◽  
Nihel Neji ◽  
Hassen Loukil ◽  
Mouhamed Ali Ben Ayed ◽  
Nouri Masmoudi
Keyword(s):  
Video Coding ◽  
High Performance ◽  
High Efficiency ◽  
High Efficiency Video Coding

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

2021 ◽  
Vol 49 (4) ◽  
pp. 1013-1027
Author(s):  
Hajar Touzani ◽  
Anass Mansouri ◽  
Fatima Errahimi ◽  
Ali Ahaitouf
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
High Efficiency Video Coding
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