Timing-aware clock gating of pulsed-latch circuits for low power design

2013 ◽  
Author(s):  
Zong-Han Yang ◽  
Tsung-Yi Ho
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Clock Gating

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 404-411
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 342-350
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor

2015 ◽  
Author(s):  
Vazgen Melikyan ◽  
Eduard Babayan ◽  
Anush Melikyan ◽  
Davit Babayan ◽  
Poghos Petrosyan ◽  
...  
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Design Methods ◽  
Clock Gating ◽  
28 Nm

scholarly journals Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops

2020 ◽  
Vol 2020 ◽  
pp. 1-9
Author(s):  
Lamjed Touil ◽  
Abdelaziz Hamdi ◽  
Ismail Gassoumi ◽  
Abdellatif Mtibaa
Keyword(s):  
Low Power ◽  
Power Saving ◽  
Digital Signal ◽  
Low Power Design ◽  
Fir Filter ◽  
Data Driven ◽  
Clock Gating ◽  
Consumption Reduction ◽  
Essential Components ◽  
Using Data

Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving of the FIR filter. The experimental results show that the proposed FIR filter achieves 25% and 22% power consumption reduction compared to that using the conventional design.

scholarly journals A Low Power FIR Filter Design for Image Processing

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 391-397 ◽  
Author(s):  
Jun Mo Jung ◽  
Jong-Wha Chong
Keyword(s):  
Image Processing ◽  
Low Power ◽  
Filter Design ◽  
Design Method ◽  
Low Power Design ◽  
Fir Filter ◽  
Correlated Data ◽  
Clock Signal ◽  
Clock Gating ◽  
Flip Flop

In this paper, a new low power design method of the FIR filter for image processing is proposed. Because the correlation between adjacent pixels is very high in image data, the clock gating technique can be a good candidate for low power strategy. However, the conventional clock gating strategy that is applied independently to every flip-flop of the filter give rise to too much additional area overhead and couldn't get a good result in the power reduction. In our method, each tap register, which is used to delay the input data in the filter, is partitioned into two sub-registers according to the correlation characteristic of its input space. For the sub-register which highly correlated data is inputted into, the dynamic power consumption is reduced by diminishing switching activity of the clock signal. We can also reduce the additional hardware overhead by propagating the clock gating control signal of the first tap register to other tap registers. To identify the efficiency of the proposed design method, we perform the experiments on some filters that are designed in VHDL. The power estimation tool says that the proposed method can reduce the power dissipation of the filter by more than 18% compared to the conventional filter design methods.

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