An Analog Front-End Circuit for CO2 Sensor Readout in 0.18-µm CMOS Process

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

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A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea8030027 ◽

2018 ◽

Vol 8 (3) ◽

pp. 27 ◽

Cited By ~ 2

Author(s):

Avish Kosari ◽

Jacob Breiholz ◽

NingXi Liu ◽

Benton Calhoun ◽

David Wentzloff

Keyword(s):

Low Power ◽

Power Efficiency ◽

Low Noise ◽

Signal Acquisition ◽

Cmos Process ◽

Ecg Signal ◽

Ecg Monitoring ◽

Power Circuit ◽

Front End ◽

Analog Front End

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications.

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A Two Channel Analog Front end Design AFE Design with Continuous Time Σ-Δ Modulator for ECG Signal

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v8i6.pp5041-5049 ◽

2018 ◽

Vol 8 (6) ◽

pp. 5041 ◽

Cited By ~ 1

Author(s):

Mohammed Abdul Raheem ◽

K Manjunathachari

Keyword(s):

Frequency Response ◽

Research Work ◽

Cmos Process ◽

Type I ◽

Sigma Delta ◽

Front End ◽

Measured Frequency ◽

Analog Front End ◽

Measured Frequency Response ◽

Power Application

In this context, the AFE with 2-channels is described, which has high impedance for low power application of bio-medical electrical activity. The challenge in obtaining accurate recordings of biomedical signals such as EEG/ECG to study the human body in research work. This paper is to propose Multi-Vt in AFE circuit design cascaded with CT modulator. The new architecture is anticipated with two dissimilar input signals filtered from 2-channel to one modulator. In this methodology, the amplifier is low powered multi-VT Analog Front-End which consumes less power by applying dual threshold voltage. Type -I category 2 channel signals of the first mode: 50 and 150 Hz amplified from AFE are given to 2nd CT sigma-delta ADC. Depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in a 0.18 um standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in 0.18 m standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, programmable gains from 52.6 dB to 72 dB, input referred noise of 3.5 μV in the amplifier bandwidth, NEF of 3.

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A Demodulation Circuit For Analog Front End Of Passive Tag Chip

Journal of Physics Conference Series ◽

10.1088/1742-6596/2065/1/012007 ◽

2021 ◽

Vol 2065 (1) ◽

pp. 012007

Author(s):

Qinglong Li ◽

Yong Xu ◽

Qiao Li ◽

Kun Peng ◽

Xian Zhang

Keyword(s):

Noise Suppression ◽

Modulation Depth ◽

Signal Frequency ◽

Cmos Process ◽

Uhf Rfid ◽

Passive Uhf Rfid ◽

Average Value ◽

Front End ◽

Analog Front End ◽

Detection Circuit

Abstract The demodulation circuit designed in this paper is suitable for the analog front end of passive UHF RFID tag chip, which can handle ASK signals with large changes in amplitude, modulation depth and signal frequency. Its performance meets the requirements of standards ISO/IEC 18000-6C and GB/T 29768-2013. Envelope detection circuit and limiter circuit are simple in structure and do not consume power. The comparison reference voltage is taken according to the average value of the envelope high and low levels, and is less affected by the dynamic changes of the input signal. Changing the width-to-length ratio of the MOSFETs in the feedback path of the comparator can adjust the hysteresis, with strong noise suppression and controllable sensitivity. The demodulator is implemented with TSMC 0.18 μm standard CMOS process. The simulation results show that the ASK signal modulation depth that the demodulator can handle is as low as 30%, and the maximum pulse width demodulation error is only 0.43%.

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Ultra-low Power Integrated Analog Front-End for ISFET-based Sensors

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v13i3.37 ◽

2018 ◽

Vol 13 (3) ◽

pp. 1-11

Author(s):

Ronaldo Martins Da Ponte ◽

Angélica Denardi De Barros ◽

José Alexandre Diniz ◽

Fernando Rangel De Sousa

Keyword(s):

Pulse Frequency ◽

The Body ◽

Ring Oscillator ◽

Cmos Process ◽

Case Scenario ◽

Worst Case ◽

Ultra Low Power ◽

Front End ◽

Analog Front End ◽

Testing Solution

In this paper, an integrated analog front-end (AFE) to condition ISFET-based sensors is presented. This is accomplished by a pH-controlled ring oscillator (pHCO) that produces a pulse frequency-modulated signal proportional to pH of a testing solution. The AFE was designed in a 180-nm standard CMOS process and a Verilog-based model was used to aid electrochemical simulations. Sensorless measurements of the chip were carried out on the oscilloscope and results revealed a digitally-represented signal with 70 MHz/V of responsivity, under a sweeping voltage from 1.0 V to 1.2 V, and a worst-case scenario of 69.4 µW for the overall power consumption. Moreover, the circuit topology circumvents the body effect problems, suppress the use of OP-AMPs or ADCs, and allows monolithic integration.

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Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays

Sensors ◽

10.3390/s20041205 ◽

2020 ◽

Vol 20 (4) ◽

pp. 1205 ◽

Cited By ~ 2

Author(s):

Iván Zamora ◽

Eyglis Ledesma ◽

Arantxa Uranga ◽

Núria Barniol

Keyword(s):

Integrated Circuit ◽

Imaging System ◽

Ultrasonic Transducer ◽

Low Noise ◽

Oxide Semiconductor ◽

Cmos Process ◽

Axial Distance ◽

Cmos Integrated Circuit ◽

Front End ◽

Analog Front End

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

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A Charge Amplifier Based Complementary Metal–Oxide–Semiconductor Analog Front End for Piezoelectric Microphones in Hearing Aid Devices

Journal of Low Power Electronics ◽

10.1166/jolpe.2019.1615 ◽

2019 ◽

Vol 15 (3) ◽

pp. 315-322

Author(s):

Manu Chilukuri ◽

Sungyong Jung ◽

Hoon-Ju Chung

Keyword(s):

Hearing Aid ◽

Complementary Metal Oxide Semiconductor ◽

Low Noise ◽

Oxide Semiconductor ◽

Cmos Process ◽

Charge Amplifier ◽

Front End ◽

Analog Front End ◽

A Charge ◽

Cascode Current Mirror

In this paper, a low noise and low power analog front end for piezoelectric microphones used in hearing aid devices is presented. It consists of a Charge Amplifier, followed by a Variable Gain Amplifier and an Analog-to-Digital Converter. At the core of charge amplifier a two stage opamp with modified cascode current mirror is designed which achieves a gain of 93 dB and phase margin of 62°. Designed analog front end achieves an input referred noise of 0.12 μVrms and SNR of 74 dB. It consumes power of 430 μW from 1.8 V supply and occupies an area of 1.2 mm × 0.22 mm. Proposed circuit is designed and fabricated in 0.18 μm CMOS process. Designed circuit is interfaced with a sensor model of piezoelectric microphone, which mimics Ormia ochracea's auditory system, and its performance is successfully verified against simulation results.

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An analog front-end for remote sensor applications with high input common-mode rejection including a 16bit ΣΔ ADC in 0.35μm 3.3V CMOS process

Proceedings of the 30th European Solid-State Circuits Conference ◽

10.1109/esscir.2004.1356717 ◽

2004 ◽

Cited By ~ 3

Author(s):

E. Compagne ◽

S. Maulet ◽

S. Genevey

Keyword(s):

Cmos Process ◽

High Input ◽

Common Mode ◽

Sensor Applications ◽

Front End ◽

Analog Front End ◽

Remote Sensor

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CMOS Analog Front-End IC for Gas Sensors

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-wp25 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 001761-001796

Author(s):

Hyuntae Kim ◽

Bertan Bakkaloglu

Keyword(s):

Detection System ◽

Sensor Arrays ◽

Low Noise ◽

Atmospheric Pollutants ◽

Amperometric Sensor ◽

Cmos Process ◽

Current Steering ◽

Front End ◽

Analog Front End ◽

Conductometric Sensor

An electrochemical sensor readout analog front-end (AFE) IC for recording long term chemical and gas exposure is presented. The AFE readout circuit enables the detection of exhaust fumes in hazardous diesel and gasoline equipment, which helps correlate atmospheric pollutants with severe illnesses. The AFE reads out the output of eight conductometric sensor arrays and eight amperometric sensor arrays. The IC consists of a low noise potentiostat and associated 9 bits current-steering DAC for sensor stimulus, followed by the first order nested chopped ΣΔ ADC. The conductometric sensor uses a current driven approach for extracting resistance change of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage for measuring current out of the sensor after a chemical reaction. The core area for the AFE is 2.65x0.95 mm2. The IC is fabricated in 0.18μm CMOS process and achieves 91dB SNR with 1.32mW power consumption per channel from a 1.8 V supply. With digital offset storage and nested chopping, the readout IC achieves 500 μV input referred offset. In order to use the system with AFE as part of a compact badge with battery, the entire gas detection system has been designed in 3D layers with a bio sensor mounted layer, an AFE layer, power management layer, a micro controller layer, and battery.

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