Ultra low power supply voltage (0.3 V) operation with extreme high speed using bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced fast-signal-transmission shallow well

2002 ◽  
Author(s):  
A. Shibata ◽  
T. Matsuoka ◽  
S. Kakimoto ◽  
H. Kotaki ◽  
M. Nakano ◽  
...  
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Power Supply ◽  
High Speed ◽  
Supply Voltage ◽  
Signal Transmission ◽  
Dynamic Threshold ◽  
Power Supply Voltage ◽  
Ultra Low Power

High‐speed low‐power and low‐power supply voltage dynamic comparator

2015 ◽  
Vol 51 (23) ◽  
pp. 1914-1916 ◽  
Author(s):  
Daiguo Xu ◽  
Shiliu Xu ◽  
Guangbing Chen
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Speed ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Dynamic Comparator

An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage

2006 ◽  
Vol 41 (10) ◽  
pp. 2344-2353 ◽  
Author(s):  
J. Chen ◽  
L.T. Clark ◽  
T.-H. Chen
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Ultra Low Power

AlInAs/GaInAs on InP HEMTs for low power supply voltage operation of high power-added efficiency microwave amplifiers

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  
Keyword(s):  
Low Power ◽  
High Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Power Added Efficiency ◽  
Microwave Amplifiers

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

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