A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

2007 ◽  
Vol 129 (4) ◽  
pp. 473-478 ◽  
Author(s):  
J. W. Wan ◽  
W. J. Zhang ◽  
D. J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Flow Characteristics ◽  
Quantitative Relation ◽  
Package Design ◽  
Solder Bumps ◽  
Filling Time ◽  
Encapsulation Process ◽  
Advanced Packaging ◽  
Gap Height

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

Regional Segregation With Spatial Considerations-Based Analytical Filling Time Model for Non-Newtonian Power-Law Underfill Fluid in Flip-Chip Encapsulation

2019 ◽  
Vol 141 (4) ◽  
Author(s):  
Fei Chong Ng ◽  
Aizat Abas ◽  
M. Z. Abdullah
Keyword(s):  
Power Law ◽  
Flip Chip ◽  
Current Model ◽  
Process Time ◽  
Time Model ◽  
Package Design ◽  
Absolute Value ◽  
Filling Time ◽  
Underfill Flow ◽  
Encapsulation Process

Abstract This paper presents a new analytical filling time model to predict the flow of non-Newtonian underfill fluid during flip-chip encapsulation process. The current model is formulated based on the regional segregation approach, instead of the conventional porous media approximation. In this approach, the filling times were computed separately at different filling stages, before being summed up till the required filling distance. The non-Newtonian property of underfill fluid is modeled using the conventional power-law constitutive equation. Additionally, the spatial aspects of the underfill flow were incorporated into the present analysis. For instance, the evolution of underfill menisci from convex to concave was analytically developed and the contact line jump (CLJ) criterion was improved using minimal flow assumption. Upon validated with three distinct past underfill experiments, the current analytical model is found to have the best performance as it predicted the filling times with the least discrepancy among other existing filling time models. Quantitatively, the discrepancies were averagely reduced by an absolute value of at least 8.68% and 4.90%, respectively, for the first two set of validation studies. Generally, this model is particularly useful in manufacturing lines to estimate the process time of flip-chip underfill, as well as for the optimizations of process and package design.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Flip-Chip Flux Evolution

2019 ◽  
Vol 2019 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Andy Mackie ◽  
Hyoryoon Jo ◽  
Sze Pei Lim
Keyword(s):  
Flip Chip ◽  
Elevated Temperatures ◽  
High Volume ◽  
Automotive Electronics ◽  
Assembly Process ◽  
Surface Finishes ◽  
Solder Bumps ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

A Model for Underfill Viscous Flow Considering the Resistance Induced by Solder Bumps

2004 ◽  
Vol 126 (2) ◽  
pp. 186-194 ◽  
Author(s):  
Chyi-Lang Lai ◽  
Wen-Bin Young
Keyword(s):  
Flip Chip ◽  
External Pressure ◽  
Good Prediction ◽  
Parallel Plates ◽  
Rectangular Array ◽  
Chip Technology ◽  
Solder Bumps ◽  
Proposed Model ◽  
Filling Time ◽  
Underfill Flow

During the underfill process, polymers driven by either capillary force or external pressure are filled at a low speed between the chip and substrate. Current methods treated the flow in the chip cavity as a laminar flow between parallel plates, which ignored the resistance induced by the solder bumps or other obstructions. In this study, the filling flow between solder bumps was simulated by a flow through a porous media. By using the superposition of flows through parallel plates and series of rectangular ducts, permeability of the underfill flow was fully characterized by the geometric arrangement of solder bumps and flat chips. The flow resistances caused by adjacent bumps were represented in its permeability. The model proposed in this study could provide a numerical approach to approximate and simulate the undefill process for flip-chip technology. Although the proposed model is applicable for any geometric arrangement of solder bumps, rectangular-array of solder bumps layout was used first for comparison with experimental results of other article. Comparisons of the flow-front shapes and filling time with the experimental data indicated that the flow simulation obtained from the proposed model gave a good prediction for the underfill flow.

Effect of hourglass shape solder joints on underfill encapsulation process: numerical and experimental studies

2020 ◽  
Vol 32 (3) ◽  
pp. 147-156
Author(s):  
Muhammad Naqib Nashrudin ◽  
Zhong Li Gan ◽  
Aizat Abas ◽  
M.H.H. Ishak ◽  
M. Yusuf Tura Ali
Keyword(s):  
Solder Joint ◽  
Numerical Method ◽  
Flip Chip ◽  
Solder Joints ◽  
Experimental Studies ◽  
Three Dimensional ◽  
Cross Sectional ◽  
Content Type ◽  
Filling Time ◽  
Encapsulation Process

Purpose In line with the recent development of flip-chip reliability and underfill process, this paper aims to comprehensively investigate the effect of different hourglass shape solder joint on underfill encapsulation process by mean of experimental and numerical method. Design/methodology/approach Lattice Boltzmann method (LBM) numerical was used for the three-dimensional simulation of underfill process. The effects of ball grid arrays (BGA) encapsulation process in terms of filling time of the fluid were investigated. Experiments were then carried out to validate the simulation results. Findings Hourglass shape solder joint has shown the shortest filling time for underfill process compared to truncated sphere. The underfill flow obtained from both simulation and experimental results are found to be in good agreement for the BGA model studied. The findings have also shown that the filling time of Hourglass 2 with parabolic shape gives faster filling time compared to the Hourglass 1 with hemisphere angle due to bigger cross-sectional area of void between the solder joints. Practical implications This paper provides reliable insights to the effect of hourglass shape BGA on the encapsulation process that will benefit future development of BGA packages. Originality/value LBM numerical method was implemented in this research to study the flow behaviour of an encapsulation process in term of filling time of hourglass shape BGA. To date, no research has been found to simulate the hourglass shape BGA using LBM.

A cost effective PoP structure with high I/O density

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000768-000785
Author(s):  
Hongjie Wang ◽  
Weidong Huang ◽  
Fei Geng ◽  
Yuan Lu ◽  
Bo Zhang ◽  
...  
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Solder Bump ◽  
Cost Effective ◽  
Wire Bonding ◽  
Manufacturing Cost ◽  
Good Reliability ◽  
Solder Bumps ◽  
Package Size ◽  
Interconnection Structure

Package-on-package (PoP) structure is widely used in smart phones and tablets in which memory package is directly attached to the top of the application processor. As the market demands more speed and bandwidth, memory devices need more than 1000 I/Os to support future requirements. However← since the package size also becomes smaller and smaller, finer I/O pitch is absolutely required. Although using some new technology can achieve finer I/O pitch, it increases the manufacturing cost. Using traditional mature technology can reduce manufacturing cost, but has limitation in finer I/O pitch. So, it demands a reasonable balance between design, process and cost to develop an applicable PoP structure. In this paper we proposed a novel and cost effective PoP interconnection structure and a multi-layer PoP model. The PoP interconnection was formed by the solder ball on the top package connected to the solder bumps on the bottom package. The solder bump was made of a smaller solder ball attached on a Cu stud bump on the top of bottom substrate. The Cu stud bump was made through wire bonding machines and was coined so that the small solder ball can be attached to it. Using film assist molding technology, a half of the solder ball is exposed outside of molding compound, which can be connected with the solder ball of the top package through reflow process. This PoP interconnection structure was named solder bump through molding (BTM). A three layer PoP vehicle package was designed in our experiments. The top package was a wire bonding BGA, the middle and bottom packages were both flip chip BGA with BTM interconnection structure. The package size of these three packages was 10×10mm2 and ball pitch was 0.4mm. The assembly process of top package was as normal as other wire bonding BGA. The assembly processes of middle and bottom packages were as follows: The Cu stud bumps were first bonded to the top surface of the substrate using wire bonding machines. Small solder balls were attached to the top of Cu stud bumps using stencil tool and then reflowed. After solder bumps were made, all chips were flip bonded to the substrates. Then, using film assist molding and MUF technology, the chips were encapsulated and Cu stud bumps were half exposed. After all the packages were ready, the package stacking and reflow was performed one by one from top to the bottom and the overall three layer PoP was formed. C-scan test and cross section analysis showed that the encapsulation had no voids in most samples. Electrical test results showed the interconnection was good. Reliability study will be also discussed in this paper, which is still in research now. In BTM structure, both Cu stud and solder ball attach can be easily realized. The ball pitch can be 0.4mm or smaller and the process is also applicable for more layer PoP. Thus, BTM PoP structure provides a good solution considering the balance among cost, performance and manufacturing for 3D package. Acknowledgments The authors acknowledge the support of National Science and Technology Major Project (Project number：2013ZX02501003).

Underfill Flow in Flip-Chip Encapsulation Process: A Review

2021 ◽  
Author(s):  
Fei Chong Ng ◽  
Mohamad Aizat Abas
Keyword(s):  
Flip Chip ◽  
Parametric Design ◽  
Microscopic Analysis ◽  
Technological Advancement ◽  
Filling Time ◽  
Underfill Flow ◽  
Encapsulation Process ◽  
Time Determination ◽  
Reliability Issue ◽  
Analytic Skills

Abstract The scope of review of this paper focused on the pre-curing underfilling flow stage of encapsulation process. A total of 80 related works has been reviewed and being classified into process type, method employed, and objective attained. Statistically showed that the conventional capillary is the most studied underfill process, while the numerical simulation was mainly adopted. Generally, the analyses on the flow dynamic and distribution of underfill fluids in the bump array aimed for the filling time determination as well as the predictions of void occurrence. Parametric design optimization was subsequently conducted to resolve the productivity issue of long filling time and reliability issue of void occurrence. The bump pitch was found to the most investigated parameter, consistent to the miniaturization demand. To enrich the design versatility and flow visualization aspects, experimental test vehicle was innovated using imitated chip and replacement fluid, or even being scaled-up. Nonetheless, the analytical filling time models became more accurate and sophiscasted over the years, despite still being scarce in number. With the technological advancement on analysis tools and further development of analytic skills, it was believed that the future researches on underfill flow will become more comprehensive, thereby leading to the production of better packages in terms of manufacturing feasibility, performances, and reliability. Lastly, few potential future works were recommended, for instance, microscopic analysis on the bump-fluid interaction, consideration of filler particles and incorporation of artificial intelligence.

Influence of Gap Height in Flip Chip Underfill Process With Non-Newtonian Flow Between Two Parallel Plates

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
C. Y. Khor ◽  
M. Z. Abdullah ◽  
M. Abdul Mujeebu
Keyword(s):  
Pressure Drop ◽  
Flip Chip ◽  
3D Model ◽  
Fluid Dynamic ◽  
Power Law Model ◽  
Parallel Plates ◽  
Newtonian Flow ◽  
Filling Time ◽  
Gap Height ◽  
Volume Method

In this paper, the finite volume method (FVM) is used for the simulation of flip chip underfill process by considering non-Newtonian flow between two parallel plates that emulate the silicon die and the substrate. 3D model of two parallel plates of size 12.75 mm × 9.5 mm with gap heights of 5 μm, 15 μm, 25 μm, 35 μm, 45 μm, and 85 μm are developed and simulated by computational fluid dynamic (CFD) code, fluent 6.3.26. The flow is modeled by using power law model and volume of fluid (VOF) technique is applied for flow front tracking. The effect of change in height of the gap between the plates on the underfill process is mainly studied in the present work. It is observed that the gap height has significant influence on the melt filling time and pressure drop, as the gap height decreases filling time and pressure drop increase. The simulation results are compared with previous experimental results and found in good conformity.

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