Optimization of Copper Column Flip Chip Packages Incorporating a Variable Interconnect Compliance Configuration

2007 ◽  
Author(s):  
Andrew A. O. Tay ◽  
Siow Ling Ho
Keyword(s):  
Fatigue Life ◽  
Flip Chip ◽  
Solder Joints ◽  
Wafer Level ◽  
Elastic Plastic ◽  
Creep Analysis ◽  
Reliability Of Solder Joints ◽  
The Impact ◽  
Plastic Creep ◽  
Copper Column

This paper describes a parametric study of the reliability of solder joints in wafer level flip chip packages that employ copper column interconnects. In this study, the impact of the change in the compliance of the copper column interconnects on the fatigue life of the solder joints were investigated by varying the diameter of the copper column interconnects. 2-D elastic-plastic finite element analyses were carried out on packages with constant interconnect diameter as well as those with variable interconnect diameters within the same package. The effect of changing the pitch and the pad size were also studied. It was found that an effective strategy in increasing the fatigue life and hence the reliability of the solder joints is by distributing copper columns of lower compliance (greater diameter) near the center of the package and increasing the compliance of the copper columns (decreasing their diameter) towards the perimeter of the chip package. In addition, elastic-plastic-creep analysis was also performed on the packages. It was observed that the results from the elastic-plastic analysis and the elastic-plastic-creep analysis exhibit the same trend.

A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect

2006 ◽  
Vol 326-328 ◽  
pp. 533-536
Author(s):  
Chang Chun Lee ◽  
Hsiao Tung Ku ◽  
Chien Chia Chiu ◽  
Kuo Ning Chiang
Keyword(s):  
Fatigue Life ◽  
Crack Growth ◽  
Solder Joints ◽  
Interfacial Crack ◽  
Actual Condition ◽  
Wafer Level ◽  
Material Interface ◽  
Element Analysis ◽  
Prediction Technique ◽  
Reliability Of Solder Joints

The predicted fatigue life of packaging structures using conventional procedures of finite element analysis (FEA) would be higher than an actual condition as a result of the perfect bonding interface assumed in the modeling. Actually, the crack extension of the solder joints along with the bi-material interface during the thermal cycling test had been observed. And, the crack models with an assumed crack length had widely adopted which only responded to the stress distribution at that moment instead of considering the effect of the whole stress history on the crack advancement. For this reason, a node tie-release crack prediction technique integrated with a nonlinear FEA was established in this research to further estimation for the thermo-mechanical reliability of solder joints. To proof our proposed technique, a double-layer wafer level chip-scaling package (DLWLCSP) was implemented as a testing vehicle to demonstrate the difference between the solder joint reliability, which was compared to the application of conventional FEA. Combined with the fracture criterion, the predicted result of using the present technique shown a lower fatigue life of solder joints than another, which using conventional one when the phenomenon of crack growth in dummy solder joints were considered. Finally, the actual experimental test showed the similar results as presented tie-release crack prediction analysis.

416 Elastic-Plastic-Creep Analysis of Sn-3.0Ag-0.5Cu Solder Joints

2007 ◽  
Vol 2007.44 (0) ◽  
pp. 161-162
Author(s):  
Yasuhiro EJIRI ◽  
Hiroshi MINAMI ◽  
Toshihiko SAYAMA ◽  
Takeshi TAKAYANAGI ◽  
Yoshiyuki OKAMOTO ◽  
...  
Keyword(s):  
Solder Joints ◽  
Elastic Plastic ◽  
Creep Analysis ◽  
Plastic Creep

1512 Elastic-Plastic-Creep Analysis of Solder Joints in Mini-lap Joint Type Shear Specimens

2009 ◽  
Vol 2009.22 (0) ◽  
pp. 726-727
Author(s):  
Hiroyuki NAKANO ◽  
Takao MORI ◽  
Toshihiko SAYAMA ◽  
Takeshi TAKAYANAGI ◽  
Yoshiyuki OKAMOTO
Keyword(s):  
Solder Joints ◽  
Lap Joint ◽  
Elastic Plastic ◽  
Creep Analysis ◽  
Plastic Creep

Assembly Equipment Requirements for Next Generation Advanced Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann
Keyword(s):  
Capital Investment ◽  
Flip Chip ◽  
High Volume ◽  
Electrical Performance ◽  
Wafer Level ◽  
Considerable Uncertainty ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
The Impact ◽  
3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

Reliability of Underfill-Encapsulated Flip-Chips With Heat Spreaders

1998 ◽  
Vol 120 (4) ◽  
pp. 322-327 ◽  
Author(s):  
H. Doi ◽  
K. Kawano ◽  
A. Yasukawa ◽  
T. Sato
Keyword(s):  
Mechanical Properties ◽  
Fatigue Life ◽  
Thermal Cycling ◽  
Failure Mode ◽  
Flip Chip ◽  
Solder Joints ◽  
Alumina Substrate ◽  
Heat Spreader ◽  
Flip Chips ◽  
Heat Spreaders

The effect of a heat spreader on the life of the solder joints for underfill-encapsulated, flip-chip packages is investigated through stress analyses and thermal cycling tests. An underfill with suitable mechanical properties is found to be able to prolong the fatigue life of the solder joints even in a package with a heat spreader and an alumina substrate. The delamination of the underfill from the chip is revealed as another critical failure mode for which the shape of the underfill fillet has a large effect.

The Effects of Temperature Cyclic Loading on Lead-Free Solder Joints of Wafer Level Chip Scale Package by Taguchi Method

2008 ◽  
Vol 130 (1) ◽  
Author(s):  
Wen-Ren Jong ◽  
Hsin-Chun Tsai ◽  
Hsiu-Tao Chang ◽  
Shu-Hui Peng
Keyword(s):  
Low Temperature ◽  
Shear Strain ◽  
Solder Joints ◽  
Strain Range ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Free Solder ◽  
Plastic Creep

In this study, the effects of the temperature cyclic loading on three lead-free solder joints of 96.5Sn–3.5Ag, 95.5Sn–3.8Ag-0.7Cu, and 95.5Sn–3.9Ag-0.6Cu bumped wafer level chip scale package (WLCSP) on printed circuit board assemblies are investigated by Taguchi method. The orthogonal arrays of L16 is applied to examine the shear strain effects of solder joints under five temperature loading parameters of the temperature ramp rate, the high and low temperature dwells, and the dwell time of both high and low temperatures by means of three simulated analyses of creep, plastic, and plastic-creep behavior on the WLCSP assemblies. It is found that the temperature dwell is the most significant factor on the effects of shear strain range from these analyses. The effect of high temperature dwell on the shear strain range is larger than that of low temperature dwell in creep analysis, while the effect of high temperature dwell on the shear strain range is smaller than that of low temperature dwell in both plastic and plastic-creep analyses.

Analysis of Stress Distribution in SnAgCu Solder Joint

2006 ◽  
Vol 5-6 ◽  
pp. 359-366 ◽  
Author(s):  
J. Gong ◽  
C. Liu ◽  
P.P. Conway ◽  
Vadim V. Silberschmidt
Keyword(s):  
Residual Stresses ◽  
Flip Chip ◽  
Solder Joints ◽  
Electronic Packages ◽  
Snagcu Solder ◽  
Snpb Solder ◽  
Creep Fatigue ◽  
Element Approach ◽  
Reliability Of Solder Joints ◽  
Free Material

SnAgCu solder is a promising lead-free material for interconnections in electronic packages. However, its melting temperature (490°K) is considerably higher than that of the traditional SnPb solder (456°K). At the same time, SnAgCu has much better creep resistance at high temperature. These properties may cause large residual stresses during manufacturing processes due to the mismatch of thermal properties of electronic components that can influence the reliability of solder joints in electronic packages. This paper studies the residual stresses in solder joints in a flip chip package under different cooling conditions and their influence on the subsequent cyclic test by means of a finite element approach. The results show that the initial temperature of 453°K is high enough to induce residual stresses due to manufacturing procedures. Simulations, based on traditional creep-fatigue models, demonstrate that the residual stresses affect the mechanical behaviour of solder joints in several initial thermal cycles but have little effect on their reliability.

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