Effect of surface polymerization on plasma and process stability in polycrystalline-silicon etching

2002 ◽  
Vol 20 (6) ◽  
pp. 2123 ◽  
Author(s):  
Songlin Xu ◽  
Thorsten Lill ◽  
Shashank Deshmukh ◽  
Olivier Joubert
Keyword(s):  
Polycrystalline Silicon ◽  
Silicon Etching ◽  
Process Stability ◽  
Surface Polymerization ◽  
Effect Of Surface

Feature evolution during plasma etching. II. Polycrystalline silicon etching

2000 ◽  
Vol 18 (1) ◽  
pp. 188-196 ◽  
Author(s):  
J. M. Lane ◽  
F. P. Klemens ◽  
K. H. A. Bogart ◽  
M. V. Malyshev ◽  
J. T. C. Lee
Keyword(s):  
Plasma Etching ◽  
Polycrystalline Silicon ◽  
Silicon Etching ◽  
Feature Evolution

Improvement of Pattern-to-Pattern Critical Dimension Variation by Model Based Method in Gate Polycrystalline Silicon Etching Process

2009 ◽  
Vol 48 (8) ◽  
pp. 08HC02
Author(s):  
Koji Tamura ◽  
Tasuku Yoshioka ◽  
Kiyoshige Ohmori ◽  
Hiroshi Yamauchi ◽  
Masayuki Sato ◽  
...  
Keyword(s):  
Polycrystalline Silicon ◽  
Critical Dimension ◽  
Etching Process ◽  
Silicon Etching ◽  
Model Based

Effect of Surface Oxidation on Polycrystalline Silicon for Photovoltaic Application

1991 ◽  
pp. 217-222 ◽  
Author(s):  
I. Delidais ◽  
D. Ballutaud ◽  
A. Boutry-Forveille ◽  
J.-L. Maurice ◽  
A. Zozime ◽  
...  
Keyword(s):  
Polycrystalline Silicon ◽  
Surface Oxidation ◽  
Photovoltaic Application ◽  
Effect Of Surface

Investigations on the Wire Bonding Capability on Selective Laser Melted Structures

2016 ◽  
Vol 2016 (1) ◽  
pp. 000209-000213
Author(s):  
Christopher Kaestle ◽  
Aarief Syed-Khaja ◽  
Joerg Franke
Keyword(s):  
Cross Sections ◽  
Flexible Manufacturing ◽  
Microscopic Analysis ◽  
Wire Bonding ◽  
Post Processing ◽  
Process Stability ◽  
The Wire ◽  
Process Combination ◽  
Non Destructive ◽  
Effect Of Surface

Abstract The paper displays the influencing factors, as well as the possibilities and challenges that come along with the process combination of selective laser melting (SLM) and heavy wire bonding. For the investigations, test samples were created from bronze powder on a SLM-machine. Then, 300 μm aluminum and copper wires were bonded on the SLM generated structures. Wire bonding capability is analyzed on untreated as well as on post-processed surfaces. The influence and effectiveness of various steps of post-processing such as cleaning, sandblasting and grinding are analyzed. Thus, interdependencies between both manufacturing process as well as the post-processing can be revealed. The effect of surface roughness and hardness of the assembly partner are investigated as well. To draw statistically backed conclusions, all tests are performed using DoE (Design of Experiment) studies. The primary characteristics besides the bond parameters that influence the wire bonding capability are focused in this paper. The process stability as well as the interconnection quality are evaluated by optical non-destructive laser microscopic analysis. Destructive pull and shear tests and metallographic cross sections are performed to evaluate the adhesion characteristics. The process stability and the yield obtained are important factors to describe the process and to evaluate the industrialization potential. By a profound understanding of all interdependencies between the two processes, a flexible manufacturing technology for power devices can be established.

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Nucleation and initial growth of Pd2Si crystals on Si(111)

1993 ◽  
Vol 51 ◽  
pp. 844-845
Author(s):  
Xianghong Tong ◽  
Oliver Pohland ◽  
J. Murray Gibson
Keyword(s):  
High Vacuum ◽  
Dark Field ◽  
Ultra High Vacuum ◽  
Initial Growth ◽  
Surface And Interface ◽  
Dark Field Imaging ◽  
Transmission Electron ◽  
Initial Stage ◽  
Effect Of Surface

The nucleation and initial stage of Pd2Si crystals on Si(111) surface is studied in situ using an Ultra-High Vacuum (UHV) Transmission Electron Microscope (TEM). A modified JEOL 200CX TEM is used for the study. The Si(111) sample is prepared by chemical thinning and is cleaned inside the UHV chamber with base pressure of 1x10−9 τ. A Pd film of 20 Å thick is deposited on to the Si(111) sample in situ using a built-in mini evaporator. This room temperature deposited Pd film is thermally annealed subsequently to form Pd2Si crystals. Surface sensitive dark field imaging is used for the study to reveal the effect of surface and interface steps.The initial growth of the Pd2Si has three stages: nucleation, growth of the nuclei and coalescence of the nuclei. Our experiments shows that the nucleation of the Pd2Si crystal occurs randomly and almost instantaneously on the terraces upon thermal annealing or electron irradiation.

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