Supporting multithreading in configurable soft processor cores

2007 ◽  
Author(s):  
Roger Moussali ◽  
Nabil Ghanem ◽  
Mazen A. R. Saghir
Keyword(s):  
Processor Cores

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

Hybrid simulation for extensible processor cores

2012 ◽  
Author(s):  
J. Jovic ◽  
S. Yakoushkin ◽  
L. Murillo ◽  
J. Eusse ◽  
R. Leupers ◽  
...  
Keyword(s):  
Hybrid Simulation ◽  
Processor Cores

Increasing the resiliency of highly loaded systems

2020 ◽  
pp. 118-123
Author(s):  
В.А. Рудометкин
Keyword(s):  
Fault Tolerance ◽  
High Load ◽  
High Availability ◽  
Distributed Transactions ◽  
Microservice Architecture ◽  
To Receive ◽  
Processor Cores ◽  
Highly Loaded

В настоящее время большинство сервисов переходят в онлайн, что позволяет пользователям получать услугу в любое время. Высокая доступность услуги приводит к росту количества пользователей, что влечет за собой повышение нагрузки на систему, поэтому необходимо уделить особое внимание отказоустойчивости системы перед началом ее разработки. Рассматриваются основные проблемы высоконагруженных систем, способ оптимизации приложения путем распараллеливания задач по ядрам процессора. В данной статье описывается необходимость перехода на микросервисную архитектуру, ее недостатки и способы их устранения. В процессе решения проблем масштабирования, затрагиваются проблемы распределенных транзакций и долгого ответа от сервера. Nowadays, most of the services are moving online, which allows users to receive the service at any time. The high availability of the service leads to an increase in the number of users, which entails an increase in the load on the system, therefore, it is necessary to pay special attention to the fault tolerance of the system before starting its development. The main problems of high-load systems, a way to optimize an application by parallelizing tasks across processor cores are considered. This article describes the need to migrate to a microservice architecture, its weaknesses, and how to fix them. In the process of solving scaling problems, the problems of distributed transactions and long response from the server are addressed.

scholarly journals Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

2021 ◽  
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Test Data ◽  
Dynamic Reconfiguration ◽  
Experimental Results ◽  
Testing Time ◽  
Industrial Testing ◽  
Difficult Condition ◽  
Optimization Methodology ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction

This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

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