A high performance hardware architecture for the H.264/AVC half-pixel motion estimation refinement

2010 ◽  
Author(s):  
Marcel Moscarelli Corrêa ◽  
Mateus Thurow Schoenknecht ◽  
Luciano Volcan Agostini
Keyword(s):  
Motion Estimation ◽  
High Performance ◽  
Hardware Architecture

A high performance hardware architecture for multi-frame hierarchical motion estimation

2011 ◽  
Vol 57 (2) ◽  
pp. 794-801 ◽  
Author(s):  
Huong Ho ◽  
Robert Klepko ◽  
Nam Ninh ◽  
Demin Wang
Keyword(s):  
Motion Estimation ◽  
High Performance ◽  
Hardware Architecture

scholarly journals A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos

2011 ◽  
Vol 2011 ◽  
pp. 1-9 ◽  
Author(s):  
Marcel M. Corrêa ◽  
Mateus T. Schoenknecht ◽  
Robson S. Dornelles ◽  
Luciano V. Agostini
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
High Throughput ◽  
High Performance ◽  
Hardware Architecture ◽  
Interpolation Process ◽  
High Definition ◽  
Efficient Search ◽  
Xilinx Fpga ◽  
Very High

This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV () in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The interpolation process is interleaved with the SAD calculation and comparison, allowing the high throughput. The architecture was fully described in VHDL, synthesized for two different Xilinx FPGA devices, and it achieved very good results when compared to related works.

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